add MISSING.md and correct missing.txt in intrinsic test

crates/core_arch/MISSING.md

@@ -0,0 +1,194 @@
+## The following neon instructions are currently not implemented in stdarch
+
+### Can be implemented next:
+
+`vcls_u16`
+
+`vcls_u32`
+
+`vcls_u8`
+
+`vclsq_u16`
+
+`vclsq_u32`
+
+`vclsq_u8`
+
+`vcreate_s16`
+
+`vcreate_u16`
+
+`vpaddq_s64`
+
+`vpaddq_u64`
+
+`vreinterpretq_p128_f32`
+
+`vreinterpretq_p128_f64`
+
+`vreinterpretq_p128_p16`
+
+`vreinterpretq_p128_p8`
+
+`vreinterpretq_p128_s16`
+
+`vreinterpretq_p128_s32`
+
+`vreinterpretq_p128_s64`
+
+`vreinterpretq_p128_s8`
+
+`vreinterpretq_p128_u16`
+
+`vreinterpretq_p128_u32`
+
+`vreinterpretq_p128_u64`
+
+`vreinterpretq_p128_u8`
+
+`vslid_n_s64`
+
+`vslid_n_u64`
+
+`vsrid_n_s64`
+
+`vsrid_n_u64`
+
+### Not implemented on arm:
+
+`vcadd_rot270_f32`
+
+`vcadd_rot90_f32`
+
+`vcaddq_rot270_f32`
+
+`vcaddq_rot90_f32`
+
+`vdot_s32`
+
+`vdot_u32`
+
+`vdotq_s32`
+
+`vdotq_u32`
+
+`vdot_lane_s32`
+
+`vdot_lane_u32`
+
+`vdotq_lane_s32`
+
+`vdotq_lane_u32`
+
+`vcmla_f32`
+
+`vcmla_lane_f32`
+
+`vcmla_laneq_f32`
+
+`vcmla_rot180_f32`
+
+`vcmla_rot180_lane_f32`
+
+`vcmla_rot180_laneq_f32`
+
+`vcmla_rot270_f32`
+
+`vcmla_rot270_lane_f32`
+
+`vcmla_rot270_laneq_f32`
+
+`vcmla_rot90_f32`
+
+`vcmla_rot90_lane_f32`
+
+`vcmla_rot90_laneq_f32`
+
+`vcmlaq_f32`
+
+`vcmlaq_lane_f32`
+
+`vcmlaq_laneq_f32`
+
+`vcmlaq_rot180_f32`
+
+`vcmlaq_rot180_lane_f32`
+
+`vcmlaq_rot180_laneq_f32`
+
+`vcmlaq_rot270_f32`
+
+`vcmlaq_rot270_lane_f32`
+
+`vcmlaq_rot270_laneq_f32`
+
+`vcmlaq_rot90_f32`
+
+`vcmlaq_rot90_lane_f32`
+
+`vcmlaq_rot90_laneq_f32`
+
+### Not implemented in LLVM:
+
+`vrnd32x_f64`
+
+`vrnd32xq_f64`
+
+`vrnd32z_f64`
+
+`vrnd32zq_f64`
+
+`vrnd64x_f64`
+
+`vrnd64xq_f64`
+
+`vrnd64z_f64`
+
+`vrnd64zq_f64`
+
+### LLVM Select errors may occur:
+
+`vsudot_lane_s32`
+
+`vsudot_laneq_s32`
+
+`vsudotq_lane_s32`
+
+`vsudotq_laneq_s32`
+
+`vusdot_lane_s32`
+
+`vusdot_laneq_s32`
+
+`vusdot_s32`
+
+`vusdotq_lane_s32`
+
+`vusdotq_laneq_s32`
+
+`vusdotq_s32v`
+
+`vqshlu_n_s16`
+
+`vqshlu_n_s32`
+
+`vqshlu_n_s64`
+
+`vqshlu_n_s8`
+
+`vqshlub_n_s8`
+
+`vqshlud_n_s64`
+
+`vqshluh_n_s16`
+
+`vqshluq_n_s16`
+
+`vqshluq_n_s32`
+
+`vqshluq_n_s64`
+
+`vqshluq_n_s8`
+
+`vqshlus_n_s32`
+

crates/intrinsic-test/missing.txt

@@ -1,19 +1,10 @@
-vmmlaq_s32
-vmmlaq_u32
 vrnd32x_f64
 vrnd32xq_f64
 vrnd32z_f64
 vrnd32zq_f64
 vrnd64x_f64
 vrnd64z_f64
 vrnd64zq_f64
-vsm3partw1q_u32
-vsm3partw2q_u32
-vsm3tt1bq_u32
-vsm3tt2aq_u32
-vsm3tt2bq_u32
-vsm4ekeyq_u32
-vsm4eq_u32
 vsudot_lane_s32
 vsudot_laneq_s32
 vsudotq_lane_s32
@@ -46,7 +37,6 @@ vqshluq_n_s32
 vqshluq_n_s64
 vqshluq_n_s8
 vqshlus_n_s32
-vrax1q_u64
 vreinterpretq_p128_f32
 vreinterpretq_p128_f64
 vreinterpretq_p128_p16
@@ -59,49 +49,17 @@ vreinterpretq_p128_u16
 vreinterpretq_p128_u32
 vreinterpretq_p128_u64
 vreinterpretq_p128_u8
-vrnd32x_f32
-vrnd32xq_f32
-vrnd32z_f32
-vrnd32zq_f32
-vrnd64x_f32
-vrnd64xq_f32
 vrnd64xq_f64
-vrnd64z_f32
-vrnd64zq_f32
-vsha512h2q_u64
-vsha512hq_u64
-vsha512su0q_u64
-vsha512su1q_u64
 vslid_n_s64
 vslid_n_u64
-vsm3ss1q_u32
-vsm3tt1aq_u32
 vsrid_n_s64
 vsrid_n_u64
-vusmmlaq_s32
-vxarq_u64
 vadd_p16
 vadd_p64
 vadd_p8
 vaddq_p16
 vaddq_p64
 vaddq_p8
-vbcaxq_s16
-vbcaxq_s32
-vbcaxq_s64
-vbcaxq_s8
-vbcaxq_u16
-vbcaxq_u32
-vbcaxq_u64
-vbcaxq_u8
-veor3q_s16
-veor3q_s32
-veor3q_s64
-veor3q_s8
-veor3q_u16
-veor3q_u32
-veor3q_u64
-veor3q_u8
 vshld_s64
 vshld_u64
 vcopyq_laneq_u8