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adamgemmelladamgemmell
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Rustfmt style changes
1 parent 6a3b07b commit cf5fb09

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4 files changed

+96
-69
lines changed

4 files changed

+96
-69
lines changed

‎crates/std_detect/src/detect/os/freebsd/auxvec.rs

+8-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,12 @@
11
//! Parses ELF auxiliary vectors.
2-
#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm", target_arch = "powerpc64"), allow(dead_code))]
2+
#![cfg_attr(
3+
any(
4+
target_arch = "aarch64",
5+
target_arch = "arm",
6+
target_arch = "powerpc64"
7+
),
8+
allow(dead_code)
9+
)]
310

411
/// Key to access the CPU Hardware capabilities bitfield.
512
pub(crate) const AT_HWCAP: usize = 25;

‎crates/std_detect/src/detect/os/linux/aarch64.rs

+74-65
Original file line numberDiff line numberDiff line change
@@ -24,57 +24,57 @@ pub(crate) fn detect_features() -> cache::Initializer {
2424
///
2525
/// [hwcap]: https://github.com/torvalds/linux/blob/master/arch/arm64/include/uapi/asm/hwcap.h
2626
struct AtHwcap {
27-
fp: bool, // 0
28-
asimd: bool, // 1
29-
// evtstrm: bool, // 2 No LLVM support
30-
aes: bool, // 3
31-
pmull: bool, // 4
32-
sha1: bool, // 5
33-
sha2: bool, // 6
34-
crc32: bool, // 7
35-
atomics: bool, // 8
36-
fphp: bool, // 9
37-
asimdhp: bool, // 10
38-
// cpuid: bool, // 11 No LLVM support
39-
asimdrdm: bool, // 12
40-
jscvt: bool, // 13
41-
fcma: bool, // 14
42-
lrcpc: bool, // 15
43-
dcpop: bool, // 16
44-
sha3: bool, // 17
45-
sm3: bool, // 18
46-
sm4: bool, // 19
47-
asimddp: bool, // 20
48-
sha512: bool, // 21
49-
sve: bool, // 22
50-
fhm: bool, // 23
51-
dit: bool, // 24
52-
uscat: bool, // 25
53-
ilrcpc: bool, // 26
54-
flagm: bool, // 27
55-
ssbs: bool, // 28
56-
sb: bool, // 29
57-
paca: bool, // 30
58-
pacg: bool, // 31
59-
dcpodp: bool, // 32
60-
sve2: bool, // 33
61-
sveaes: bool, // 34
62-
// svepmull: bool, // 35 No LLVM support
27+
fp: bool, // 0
28+
asimd: bool, // 1
29+
// evtstrm: bool, // 2 No LLVM support
30+
aes: bool, // 3
31+
pmull: bool, // 4
32+
sha1: bool, // 5
33+
sha2: bool, // 6
34+
crc32: bool, // 7
35+
atomics: bool, // 8
36+
fphp: bool, // 9
37+
asimdhp: bool, // 10
38+
// cpuid: bool, // 11 No LLVM support
39+
asimdrdm: bool, // 12
40+
jscvt: bool, // 13
41+
fcma: bool, // 14
42+
lrcpc: bool, // 15
43+
dcpop: bool, // 16
44+
sha3: bool, // 17
45+
sm3: bool, // 18
46+
sm4: bool, // 19
47+
asimddp: bool, // 20
48+
sha512: bool, // 21
49+
sve: bool, // 22
50+
fhm: bool, // 23
51+
dit: bool, // 24
52+
uscat: bool, // 25
53+
ilrcpc: bool, // 26
54+
flagm: bool, // 27
55+
ssbs: bool, // 28
56+
sb: bool, // 29
57+
paca: bool, // 30
58+
pacg: bool, // 31
59+
dcpodp: bool, // 32
60+
sve2: bool, // 33
61+
sveaes: bool, // 34
62+
// svepmull: bool, // 35 No LLVM support
6363
svebitperm: bool, // 36
6464
svesha3: bool, // 37
6565
svesm4: bool, // 38
66-
// flagm2: bool, // 39 No LLVM support
67-
frint: bool, // 40
68-
// svei8mm: bool, // 41 See i8mm feature
69-
svef32mm: bool, // 42
70-
svef64mm: bool, // 43
71-
// svebf16: bool, // 44 See bf16 feature
72-
i8mm: bool, // 45
73-
bf16: bool, // 46
74-
// dgh: bool, // 47 No LLVM support
75-
rng: bool, // 48
76-
bti: bool, // 49
77-
mte: bool, // 50
66+
// flagm2: bool, // 39 No LLVM support
67+
frint: bool, // 40
68+
// svei8mm: bool, // 41 See i8mm feature
69+
svef32mm: bool, // 42
70+
svef64mm: bool, // 43
71+
// svebf16: bool, // 44 See bf16 feature
72+
i8mm: bool, // 45
73+
bf16: bool, // 46
74+
// dgh: bool, // 47 No LLVM support
75+
rng: bool, // 48
76+
bti: bool, // 49
77+
mte: bool, // 50
7878
}
7979

8080
impl From<auxvec::AuxVec> for AtHwcap {
@@ -83,7 +83,7 @@ impl From<auxvec::AuxVec> for AtHwcap {
8383
AtHwcap {
8484
fp: bit::test(auxv.hwcap, 0),
8585
asimd: bit::test(auxv.hwcap, 1),
86-
// evtstrm: bit::test(auxv.hwcap, 2),
86+
// evtstrm: bit::test(auxv.hwcap, 2),
8787
aes: bit::test(auxv.hwcap, 3),
8888
pmull: bit::test(auxv.hwcap, 4),
8989
sha1: bit::test(auxv.hwcap, 5),
@@ -92,7 +92,7 @@ impl From<auxvec::AuxVec> for AtHwcap {
9292
atomics: bit::test(auxv.hwcap, 8),
9393
fphp: bit::test(auxv.hwcap, 9),
9494
asimdhp: bit::test(auxv.hwcap, 10),
95-
// cpuid: bit::test(auxv.hwcap, 11),
95+
// cpuid: bit::test(auxv.hwcap, 11),
9696
asimdrdm: bit::test(auxv.hwcap, 12),
9797
jscvt: bit::test(auxv.hwcap, 13),
9898
fcma: bit::test(auxv.hwcap, 14),
@@ -116,19 +116,19 @@ impl From<auxvec::AuxVec> for AtHwcap {
116116
dcpodp: bit::test(auxv.hwcap, 32),
117117
sve2: bit::test(auxv.hwcap, 33),
118118
sveaes: bit::test(auxv.hwcap, 34),
119-
// svepmull: bit::test(auxv.hwcap, 35),
119+
// svepmull: bit::test(auxv.hwcap, 35),
120120
svebitperm: bit::test(auxv.hwcap, 36),
121121
svesha3: bit::test(auxv.hwcap, 37),
122122
svesm4: bit::test(auxv.hwcap, 38),
123-
// flagm2: bit::test(auxv.hwcap, 39),
123+
// flagm2: bit::test(auxv.hwcap, 39),
124124
frint: bit::test(auxv.hwcap, 40),
125-
// svei8mm: bit::test(auxv.hwcap, 41),
125+
// svei8mm: bit::test(auxv.hwcap, 41),
126126
svef32mm: bit::test(auxv.hwcap, 42),
127127
svef64mm: bit::test(auxv.hwcap, 43),
128-
// svebf16: bit::test(auxv.hwcap, 44),
128+
// svebf16: bit::test(auxv.hwcap, 44),
129129
i8mm: bit::test(auxv.hwcap, 45),
130130
bf16: bit::test(auxv.hwcap, 46),
131-
// dgh: bit::test(auxv.hwcap, 47),
131+
// dgh: bit::test(auxv.hwcap, 47),
132132
rng: bit::test(auxv.hwcap, 48),
133133
bti: bit::test(auxv.hwcap, 49),
134134
mte: bit::test(auxv.hwcap, 50),
@@ -147,7 +147,7 @@ impl From<super::cpuinfo::CpuInfo> for AtHwcap {
147147
// cover that yet.
148148
fp: f.has("fp"),
149149
asimd: f.has("asimd"),
150-
// evtstrm: f.has("evtstrm"),
150+
// evtstrm: f.has("evtstrm"),
151151
aes: f.has("aes"),
152152
pmull: f.has("pmull"),
153153
sha1: f.has("sha1"),
@@ -156,7 +156,7 @@ impl From<super::cpuinfo::CpuInfo> for AtHwcap {
156156
atomics: f.has("atomics"),
157157
fphp: f.has("fphp"),
158158
asimdhp: f.has("asimdhp"),
159-
// cpuid: f.has("cpuid"),
159+
// cpuid: f.has("cpuid"),
160160
asimdrdm: f.has("asimdrdm"),
161161
jscvt: f.has("jscvt"),
162162
fcma: f.has("fcma"),
@@ -180,19 +180,19 @@ impl From<super::cpuinfo::CpuInfo> for AtHwcap {
180180
dcpodp: f.has("dcpodp"),
181181
sve2: f.has("sve2"),
182182
sveaes: f.has("sveaes"),
183-
// svepmull: f.has("svepmull"),
183+
// svepmull: f.has("svepmull"),
184184
svebitperm: f.has("svebitperm"),
185185
svesha3: f.has("svesha3"),
186186
svesm4: f.has("svesm4"),
187-
// flagm2: f.has("flagm2"),
187+
// flagm2: f.has("flagm2"),
188188
frint: f.has("frint"),
189-
// svei8mm: f.has("svei8mm"),
189+
// svei8mm: f.has("svei8mm"),
190190
svef32mm: f.has("svef32mm"),
191191
svef64mm: f.has("svef64mm"),
192-
// svebf16: f.has("svebf16"),
192+
// svebf16: f.has("svebf16"),
193193
i8mm: f.has("i8mm"),
194194
bf16: f.has("bf16"),
195-
// dgh: f.has("dgh"),
195+
// dgh: f.has("dgh"),
196196
rng: f.has("rng"),
197197
bti: f.has("bti"),
198198
mte: f.has("mte"),
@@ -264,16 +264,25 @@ impl AtHwcap {
264264
enable_feature(Feature::aes, self.aes && asimd);
265265
enable_feature(Feature::sha2, self.sha1 && self.sha2 && asimd);
266266
// SHA512/SHA3 require SHA1 & SHA256
267-
enable_feature(Feature::sha3, self.sha512 && self.sha3 && self.sha1 && self.sha2 && asimd);
267+
enable_feature(
268+
Feature::sha3,
269+
self.sha512 && self.sha3 && self.sha1 && self.sha2 && asimd,
270+
);
268271
enable_feature(Feature::sm4, self.sm3 && self.sm4 && asimd);
269272

270273
// SVE2 requires SVE
271274
let sve2 = self.sve2 && self.sve && asimd;
272275
enable_feature(Feature::sve2, sve2);
273276
// SVE2 extensions require SVE2 and crypto features
274277
enable_feature(Feature::sve2_aes, self.sveaes && sve2 && self.aes);
275-
enable_feature(Feature::sve2_sm4, self.svesm4 && sve2 && self.sm3 && self.sm4);
276-
enable_feature(Feature::sve2_sha3, self.svesha3 && sve2 && self.sha512 && self.sha3 && self.sha1 && self.sha2);
278+
enable_feature(
279+
Feature::sve2_sm4,
280+
self.svesm4 && sve2 && self.sm3 && self.sm4,
281+
);
282+
enable_feature(
283+
Feature::sve2_sha3,
284+
self.svesha3 && sve2 && self.sha512 && self.sha3 && self.sha1 && self.sha2,
285+
);
277286
enable_feature(Feature::sve2_bitperm, self.svebitperm && self.sve2);
278287
}
279288
value

‎crates/std_detect/src/detect/os/linux/arm.rs

+10-2
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,11 @@ pub(crate) fn detect_features() -> cache::Initializer {
2222
enable_feature(&mut value, Feature::crc, bit::test(auxv.hwcap2, 4));
2323
enable_feature(&mut value, Feature::aes, bit::test(auxv.hwcap2, 0));
2424
// SHA2 requires SHA1 & SHA2 features
25-
enable_feature(&mut value, Feature::sha2, bit::test(auxv.hwcap2, 2) && bit::test(auxv.hwcap2, 3));
25+
enable_feature(
26+
&mut value,
27+
Feature::sha2,
28+
bit::test(auxv.hwcap2, 2) && bit::test(auxv.hwcap2, 3),
29+
);
2630
return value;
2731
}
2832

@@ -36,7 +40,11 @@ pub(crate) fn detect_features() -> cache::Initializer {
3640
enable_feature(&mut value, Feature::pmull, c.field("Features").has("pmull"));
3741
enable_feature(&mut value, Feature::crc, c.field("Features").has("crc32"));
3842
enable_feature(&mut value, Feature::aes, c.field("Features").has("aes"));
39-
enable_feature(&mut value, Feature::sha2, c.field("Features").has("sha1") && c.field("Features").has("sha2"));
43+
enable_feature(
44+
&mut value,
45+
Feature::sha2,
46+
c.field("Features").has("sha1") && c.field("Features").has("sha2"),
47+
);
4048
return value;
4149
}
4250
value

‎crates/std_detect/tests/cpu-detection.rs

+4-1
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,10 @@ fn aarch64_linux() {
6161
println!("sve2-aes: {}", is_aarch64_feature_detected!("sve2-aes"));
6262
println!("sve2-sm4: {}", is_aarch64_feature_detected!("sve2-sm4"));
6363
println!("sve2-sha3: {}", is_aarch64_feature_detected!("sve2-sha3"));
64-
println!("sve2-bitperm: {}", is_aarch64_feature_detected!("sve2-bitperm"));
64+
println!(
65+
"sve2-bitperm: {}",
66+
is_aarch64_feature_detected!("sve2-bitperm")
67+
);
6568
println!("frintts: {}", is_aarch64_feature_detected!("frintts"));
6669
println!("i8mm: {}", is_aarch64_feature_detected!("i8mm"));
6770
println!("f32mm: {}", is_aarch64_feature_detected!("f32mm"));

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