feature detection

Author: vertexclique

Diff for: crates/core_arch/src/aarch64/tme.rs

@@ -19,50 +19,50 @@ use stdarch_test::assert_instr;
 
 extern "C" {
     #[link_name = "llvm.aarch64.tstart"]
-    fn aarch64_tstart() -> i32;
+    fn aarch64_tstart() -> i64;
     #[link_name = "llvm.aarch64.tcommit"]
     fn aarch64_tcommit() -> ();
     #[link_name = "llvm.aarch64.tcancel"]
     fn aarch64_tcancel(imm0: i64) -> ();
     #[link_name = "llvm.aarch64.ttest"]
-    fn aarch64_ttest() -> i32;
+    fn aarch64_ttest() -> i64;
 }
 
 /// Transaction successfully started.
-pub const _TMSTART_SUCCESS: u32 = 0x00_u32;
+pub const _TMSTART_SUCCESS: i64 = 0x00_i64;
 
 /// Extraction mask for failure reason
-pub const _TMFAILURE_REASON: u32 = 0x00007FFF_u32;
+pub const _TMFAILURE_REASON: i64 = 0x00007FFF_i64;
 
 /// Transaction retry is possible.
-pub const _TMFAILURE_RTRY: u32 = 1 << 15;
+pub const _TMFAILURE_RTRY: i64 = 1 << 15;
 
 /// Transaction executed a TCANCEL instruction
-pub const _TMFAILURE_CNCL: u32 = 1 << 16;
+pub const _TMFAILURE_CNCL: i64 = 1 << 16;
 
 /// Transaction aborted because a conflict occurred
-pub const _TMFAILURE_MEM: u32 = 1 << 17;
+pub const _TMFAILURE_MEM: i64 = 1 << 17;
 
 /// Fallback error type for any other reason
-pub const _TMFAILURE_IMP: u32 = 1 << 18;
+pub const _TMFAILURE_IMP: i64 = 1 << 18;
 
 /// Transaction aborted because a non-permissible operation was attempted
-pub const _TMFAILURE_ERR: u32 = 1 << 19;
+pub const _TMFAILURE_ERR: i64 = 1 << 19;
 
 /// Transaction aborted due to read or write set limit was exceeded
-pub const _TMFAILURE_SIZE: u32 = 1 << 20;
+pub const _TMFAILURE_SIZE: i64 = 1 << 20;
 
 /// Transaction aborted due to transactional nesting level was exceeded
-pub const _TMFAILURE_NEST: u32 = 1 << 21;
+pub const _TMFAILURE_NEST: i64 = 1 << 21;
 
 /// Transaction aborted due to a debug trap.
-pub const _TMFAILURE_DBG: u32 = 1 << 22;
+pub const _TMFAILURE_DBG: i64 = 1 << 22;
 
 /// Transaction failed from interrupt
-pub const _TMFAILURE_INT: u32 = 1 << 23;
+pub const _TMFAILURE_INT: i64 = 1 << 23;
 
 /// Indicates a TRIVIAL version of TM is available
-pub const _TMFAILURE_TRIVIAL: u32 = 1 << 24;
+pub const _TMFAILURE_TRIVIAL: i64 = 1 << 24;
 
 /// Starts a new transaction. When the transaction starts successfully the return value is 0.
 /// If the transaction fails, all state modifications are discarded and a cause of the failure
@@ -72,7 +72,7 @@ pub const _TMFAILURE_TRIVIAL: u32 = 1 << 24;
 #[inline]
 #[target_feature(enable = "tme")]
 #[cfg_attr(test, assert_instr(tstart))]
-pub unsafe fn __tstart() -> u32 {
+pub unsafe fn __tstart() -> i64 {
     aarch64_tstart() as _
 }
 
@@ -95,7 +95,7 @@ pub unsafe fn __tcommit() {
 #[target_feature(enable = "tme")]
 #[cfg_attr(test, assert_instr(tcancel, imm0 = 0x0))]
 #[rustc_args_required_const(0)]
-pub unsafe fn __tcancel(imm0: u32) {
+pub unsafe fn __tcancel(imm0: i64) {
     macro_rules! call {
         ($imm0:expr) => {
             aarch64_tcancel($imm0)
@@ -111,7 +111,7 @@ pub unsafe fn __tcancel(imm0: u32) {
 #[inline]
 #[target_feature(enable = "tme")]
 #[cfg_attr(test, assert_instr(ttest))]
-pub unsafe fn __ttest() -> u32 {
+pub unsafe fn __ttest() -> i64 {
     aarch64_ttest() as _
 }
 
@@ -121,14 +121,16 @@ mod tests {
 
     use crate::core_arch::aarch64::*;
 
+    const CANCEL_CODE: i64 = (0 | (0x123 & _TMFAILURE_REASON) as i64) as i64;
+
     #[simd_test(enable = "tme")]
     unsafe fn test_tstart() {
         let mut x = 0;
         for i in 0..10 {
             let code = tme::__tstart();
             if code == _TMSTART_SUCCESS {
                 x += 1;
-                assert_eq!(x, i+1);
+                assert_eq!(x, i + 1);
                 break;
             }
             assert_eq!(x, 0);
@@ -142,25 +144,23 @@ mod tests {
             let code = tme::__tstart();
             if code == _TMSTART_SUCCESS {
                 x += 1;
-                assert_eq!(x, i+1);
+                assert_eq!(x, i + 1);
                 tme::__tcommit();
             }
-            assert_eq!(x, i+1);
+            assert_eq!(x, i + 1);
         }
     }
 
     #[simd_test(enable = "tme")]
     unsafe fn test_tcancel() {
-        let reason = 0x123;
-        let cancel_code = (0 | (reason & _TMFAILURE_REASON) as i32) as u32;
         let mut x = 0;
 
         for i in 0..10 {
             let code = tme::__tstart();
             if code == _TMSTART_SUCCESS {
                 x += 1;
-                assert_eq!(x, i+1);
-                tme::__tcancel(cancel_code);
+                assert_eq!(x, i + 1);
+                tme::__tcancel(CANCEL_CODE);
                 break;
             }
         }
@@ -170,14 +170,12 @@ mod tests {
 
     #[simd_test(enable = "tme")]
     unsafe fn test_ttest() {
-        let reason = 0x123;
-        let cancel_code = (0 | (reason & _TMFAILURE_REASON) as i32) as u32;
         for _ in 0..10 {
             let code = tme::__tstart();
             if code == _TMSTART_SUCCESS {
                 if tme::__ttest() == 2 {
-              	     tme::__tcancel(cancel_code);
-                  	 break;
+                    tme::__tcancel(CANCEL_CODE);
+                    break;
                 }
             }
         }

Diff for: crates/simd-test-macro/src/lib.rs

@@ -156,5 +156,8 @@ fn find_name(item: TokenStream) -> Ident {
         }
     }
 
-    tokens.next().and_then(get_ident).expect("failed to find function name")
+    tokens
+        .next()
+        .and_then(get_ident)
+        .expect("failed to find function name")
 }

Diff for: crates/std_detect/src/detect/arch/aarch64.rs

@@ -33,4 +33,6 @@ features! {
     /// Release consistent Processor consistent (RcPc)
     @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] dotprod: "dotprod";
     /// Vector Dot-Product (ASIMDDP)
+    @FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] tme: "tme";
+    /// Transactional Memory Extensions (TME)
 }

Diff for: crates/std_detect/src/detect/os/aarch64.rs

@@ -44,6 +44,7 @@ pub(crate) fn detect_features() -> cache::Initializer {
         enable_feature(Feature::pmull, pmull);
         // Crypto is specified as AES + PMULL + SHA1 + SHA2 per LLVM/hosts.cpp
         enable_feature(Feature::crypto, aes && pmull && sha1 && sha2);
+        enable_feature(Feature::tme, bits_shift(aa64isar0, 27, 24) == 1);
         enable_feature(Feature::lse, bits_shift(aa64isar0, 23, 20) >= 1);
         enable_feature(Feature::crc, bits_shift(aa64isar0, 19, 16) >= 1);
 

Diff for: crates/std_detect/src/detect/os/freebsd/aarch64.rs

@@ -17,5 +17,6 @@ mod tests {
         println!("rdm: {:?}", is_aarch64_feature_detected!("rdm"));
         println!("rcpc: {:?}", is_aarch64_feature_detected!("rcpc"));
         println!("dotprod: {:?}", is_aarch64_feature_detected!("dotprod"));
+        println!("tme: {:?}", is_aarch64_feature_detected!("tme"));
     }
 }