Move entirely to array-based SIMD

See MCP#621

This tries to make as few changes as possible -- it keeps the `new` functions taking all the parameters, for example.

Author: scottmcm

crates/core_arch/src/aarch64/neon/mod.rs

@@ -23,10 +23,10 @@ use stdarch_test::assert_instr;
 types! {
     /// ARM-specific 64-bit wide vector of one packed `f64`.
     #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-    pub struct float64x1_t(f64); // FIXME: check this!
+    pub struct float64x1_t(1 x f64); // FIXME: check this!
     /// ARM-specific 128-bit wide vector of two packed `f64`.
     #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-    pub struct float64x2_t(f64, f64);
+    pub struct float64x2_t(2 x f64);
 }
 
 /// ARM-specific type containing two `float64x1_t` vectors.
@@ -1061,7 +1061,7 @@ pub unsafe fn vabsq_s64(a: int64x2_t) -> int64x2_t {
 #[cfg_attr(test, assert_instr(bsl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub unsafe fn vbsl_f64(a: uint64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
-    let not = int64x1_t(-1);
+    let not = int64x1_t([-1; 1]);
     transmute(simd_or(
         simd_and(a, transmute(b)),
         simd_and(simd_xor(a, transmute(not)), transmute(c)),
@@ -1073,7 +1073,7 @@ pub unsafe fn vbsl_f64(a: uint64x1_t, b: float64x1_t, c: float64x1_t) -> float64
 #[cfg_attr(test, assert_instr(bsl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub unsafe fn vbsl_p64(a: poly64x1_t, b: poly64x1_t, c: poly64x1_t) -> poly64x1_t {
-    let not = int64x1_t(-1);
+    let not = int64x1_t([-1; 1]);
     simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c))
 }
 /// Bitwise Select. (128-bit)
@@ -1082,7 +1082,7 @@ pub unsafe fn vbsl_p64(a: poly64x1_t, b: poly64x1_t, c: poly64x1_t) -> poly64x1_
 #[cfg_attr(test, assert_instr(bsl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub unsafe fn vbslq_f64(a: uint64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t {
-    let not = int64x2_t(-1, -1);
+    let not = int64x2_t([-1; 2]);
     transmute(simd_or(
         simd_and(a, transmute(b)),
         simd_and(simd_xor(a, transmute(not)), transmute(c)),
@@ -1094,7 +1094,7 @@ pub unsafe fn vbslq_f64(a: uint64x2_t, b: float64x2_t, c: float64x2_t) -> float6
 #[cfg_attr(test, assert_instr(bsl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub unsafe fn vbslq_p64(a: poly64x2_t, b: poly64x2_t, c: poly64x2_t) -> poly64x2_t {
-    let not = int64x2_t(-1, -1);
+    let not = int64x2_t([-1; 2]);
     simd_or(simd_and(a, b), simd_and(simd_xor(a, transmute(not)), c))
 }
 
@@ -1994,7 +1994,7 @@ pub unsafe fn vdupq_n_p64(value: p64) -> poly64x2_t {
 #[cfg_attr(test, assert_instr(dup))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub unsafe fn vdupq_n_f64(value: f64) -> float64x2_t {
-    float64x2_t(value, value)
+    float64x2_t([value; 2])
 }
 
 /// Duplicate vector element to vector or scalar

crates/core_arch/src/arm/dsp.rs

@@ -28,10 +28,10 @@ use crate::mem::transmute;
 types! {
     /// ARM-specific 32-bit wide vector of two packed `i16`.
     #[unstable(feature = "stdarch_arm_dsp", issue = "117237")]
-    pub struct int16x2_t(i16, i16);
+    pub struct int16x2_t(2 x i16);
     /// ARM-specific 32-bit wide vector of two packed `u16`.
     #[unstable(feature = "stdarch_arm_dsp", issue = "117237")]
-    pub struct uint16x2_t(u16, u16);
+    pub struct uint16x2_t(2 x u16);
 }
 
 extern "unadjusted" {