Start creating abstractions for APIC registers

Author: phil-opp

Cargo.toml

@@ -4,6 +4,6 @@ version = "0.1.0"
 authors = ["Philipp Oppermann <dev@phil-opp.com>"]
 edition = "2018"
 
-# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
-
 [dependencies]
+bit_field = "0.10.1"
+volatile = "0.4.0-alpha"

rust-toolchain

@@ -0,0 +1 @@
+nightly

src/lib.rs

@@ -1,7 +1,85 @@
-#[cfg(test)]
-mod tests {
-    #[test]
-    fn it_works() {
-        assert_eq!(2 + 2, 4);
+#![no_std]
+#![feature(unsafe_block_in_unsafe_fn)]
+#![deny(unsafe_op_in_unsafe_fn)]
+
+use volatile::Volatile;
+
+pub mod registers;
+
+pub struct ApicRegisters {
+    base_addr: *mut (),
+}
+
+impl ApicRegisters {
+    pub fn id(&mut self) -> Volatile<&mut registers::Id> {
+        unsafe { self.offset(Offset::Id) }
+    }
+
+    pub fn version(&mut self) -> Volatile<&mut registers::Version> {
+        unsafe { self.offset(Offset::Version) }
+    }
+
+    pub fn extended_apic_feature(&mut self) -> Volatile<&mut registers::ExtendedApicFeature> {
+        unsafe { self.offset(Offset::ExtendedApicFeature) }
     }
+
+    pub fn extended_apic_control(&mut self) -> Volatile<&mut registers::ExtendedApicControl> {
+        unsafe { self.offset(Offset::ExtendedApicControl) }
+    }
+
+    /*
+        pub fn task_priority(&mut self) -> Volatile<&mut registers::TaskPriority> {
+            unsafe { self.offset(Offset::TaskPriority) }
+        }
+
+        pub fn arbitration_priority(&mut self) -> Volatile<&mut registers::ArbitrationPriority> {
+            unsafe { self.offset(Offset::ArbitrationPriority) }
+        }
+
+        pub fn processor_priority(&mut self) -> Volatile<&mut registers::ProcessorPriority> {
+            unsafe { self.offset(Offset::ProcessorPriority) }
+        }
+
+        pub fn end_of_interrupt(&mut self) -> Volatile<&mut registers::EndOfInterrupt> {
+            unsafe { self.offset(Offset::EndOfInterrupt) }
+        }
+    */
+
+    unsafe fn offset<T>(&mut self, offset: Offset) -> Volatile<&mut T> {
+        let ptr = self.base_addr.wrapping_add(offset as usize).cast();
+        Volatile::new(unsafe { &mut *ptr })
+    }
+}
+
+#[repr(usize)]
+pub enum Offset {
+    Id = 0x20,
+    Version = 0x30,
+    TaskPriority = 0x80,
+    ArbitrationPriority = 0x90,
+    ProcessorPriority = 0xa0,
+    EndOfInterrupt = 0xb0,
+    RemoteRead = 0xc0,
+    LocalDestination = 0xd0,
+    DestinationFormat = 0xe0,
+    SpuriousInterruptVector = 0xf0,
+    InService = 0x100,
+    TriggerMode = 0x180,
+    InterruptRequest = 0x200,
+    ErrorStatus = 0x280,
+    InterruptCommand = 0x300,
+    TimerLocalVectorTableEntry = 0x320,
+    ThermalLocalVectorTableEntry = 0x330,
+    PerformanceCounterLocalVectorTableEntry = 0x340,
+    LocalInterrupt0VectorTableEntry = 0x350,
+    LocalInterrupt1VectorTableEntry = 0x360,
+    ErrorVectorTableEntry = 0x370,
+    TimerInitialCount = 0x380,
+    TimerCurrentCount = 0x390,
+    TimerDivideConfiguration = 0x3e0,
+    ExtendedApicFeature = 0x400,
+    ExtendedApicControl = 0x410,
+    SpecificEndOfInterrupt = 0x420,
+    InterruptEnable = 0x480,
+    ExtendedInterruptLocalVectorTable = 0x500,
 }

src/registers.rs

@@ -0,0 +1,91 @@
+use core::convert::TryInto;
+
+use bit_field::BitField;
+
+#[derive(Debug, Copy, Clone)]
+#[repr(transparent)]
+pub struct Id(u32);
+
+impl Id {
+    /// Returns the unique APIC ID value assigned to this specific CPU core
+    pub fn id(&self) -> u8 {
+        self.0.get_bits(24..).try_into().unwrap()
+    }
+}
+
+#[derive(Debug, Copy, Clone)]
+#[repr(transparent)]
+pub struct Version(u32);
+
+impl Version {
+    /// Indicates  the  version  number  of  the  APIC implementation
+    pub fn version(&self) -> u8 {
+        self.0.get_bits(..8).try_into().unwrap()
+    }
+
+    /// Specifies the number of entries in the localvector table minus one
+    pub fn max_lvt_entries(&self) -> u8 {
+        self.0.get_bits(16..24).try_into().unwrap()
+    }
+
+    /// Indicates thepresence of an extended APIC register space
+    pub fn extended_apic_register_space_present(&self) -> bool {
+        self.0.get_bit(31)
+    }
+}
+
+#[derive(Debug, Copy, Clone)]
+#[repr(transparent)]
+pub struct ExtendedApicFeature(u32);
+
+impl ExtendedApicFeature {
+    /// Specifies the number of extended local vector tableregisters in the local APIC
+    pub fn extended_lvt_count(&self) -> u8 {
+        self.0.get_bits(16..24).try_into().unwrap()
+    }
+
+    /// Indicates  that  the  processor  is  capable  ofsupporting an 8-bit APIC ID
+    pub fn extended_apic_id_capability(&self) -> bool {
+        self.0.get_bit(2)
+    }
+
+    /// Indicates that the Specific End Of Interrupt Register is present
+    pub fn specific_end_of_interrupt_capable(&self) -> bool {
+        self.0.get_bit(1)
+    }
+
+    /// Indicates  that  the  Interrupt  EnableRegisters are present
+    pub fn interrupt_enable_register_capable(&self) -> bool {
+        self.0.get_bit(1)
+    }
+}
+
+#[derive(Debug, Copy, Clone)]
+#[repr(transparent)]
+pub struct ExtendedApicControl(u32);
+
+impl ExtendedApicControl {
+    pub fn extended_apic_id_enabled(&self) -> bool {
+        self.0.get_bit(2)
+    }
+
+    pub fn enable_extended_apic_id(&mut self, enable: bool) {
+        self.0.set_bit(2, enable);
+    }
+
+    pub fn specific_end_of_interrupt_generation_enabled(&self) -> bool {
+        self.0.get_bit(1)
+    }
+
+    pub fn enable_specific_end_of_interrupt_generation(&mut self, enable: bool) {
+        self.0.set_bit(1, enable);
+    }
+
+    pub fn interrupt_enable_registers_enabled(&self) -> bool {
+        self.0.get_bit(0)
+    }
+
+    pub fn enable_interrupt_enable_registers(&mut self, enable: bool) {
+        self.0.set_bit(0, enable);
+    }
+}