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design.core
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design.core
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CAPI=2:
name: ::riscv-sv:0.1.0
description: Description of your design
filesets:
rtl:
files:
- src/core.sv : { file_type: systemVerilogSource }
- src/alu.sv : { file_type: systemVerilogSource }
- src/decoder.sv : { file_type: systemVerilogSource }
- src/regfile.sv : { file_type: systemVerilogSource }
- src/interfaces_pkg.sv : { file_type: systemVerilogSource }
- src/include/common_cells/registers.svh : { file_type: systemVerilogSource, is_include_file : true}
- src/include/typedef.svh : { file_type: systemVerilogSource, is_include_file : true}
- src/include/defines.svh : { file_type: systemVerilogSource, is_include_file : true}
core_tb:
files:
- testbench/tb_top.sv
file_type: systemVerilogSource
formal_files:
files:
- sbyConfig.sby.j2 : { file_type: sbyConfigTemplate }
- testbench/formal/formal_tb_frag.svh : {file_type: systemVerilogSource, is_include_file: true}
- testbench/formal/core_formal_tb.sv : {file_type: systemVerilogSource}
depend:
- lowrisc:util:sv2v
- lowrisc:prim:assert
verilator_tb:
files:
- testbench/sim_main.cpp
file_type : cppSource
targets:
default: &default_target
filesets :
- rtl
toplevel : core
sim:
default_tool : verilator
filesets :
- rtl
- core_tb
- verilator_tb
tools:
verilator:
verilator_options :
- --language 1800-2017
- --trace
- -Wno-fatal
toplevel : tb_top
lint:
default_tool : verilator
filesets :
- rtl
- core_tb
- verilator_tb
tools:
verilator:
mode : lint-only
verilator_options :
- --language 1800-2017
- --trace
- -Wno-fatal
toplevel : tb_top
formal:
default_tool : symbiyosys
filesets :
- rtl
- formal_files
tools:
symbiyosys:
tasknames:
- prove
toplevel : core