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package.json
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{
"name": "SystemVerilog",
"description": "System Verilog support for VS Code",
"version": "0.0.16",
"publisher": "mshr-h",
"repository": {
"type": "git",
"url": "https://github.com/mshr-h/vscode-systemverilog-support.git"
},
"engines": {
"vscode": "^1.10.0"
},
"categories": [
"Languages"
],
"contributes": {
"languages": [
{
"id": "systemverilog",
"aliases": [
"System Verilog",
"systemverilog"
],
"extensions": [
".sv",
".SV"
],
"configuration": "./language-configuration.json"
}
],
"grammars": [
{
"language": "systemverilog",
"scopeName": "source.systemverilog",
"path": "./syntaxes/systemverilog.tmLanguage"
}
],
"snippets": [
{
"language": "systemverilog",
"path": "./snippets/snippets.json"
}
],
"configuration": {
"title": "",
"properties": {
"systemverilog.instancePrefix": {
"type": "string",
"default": "u_",
"description": "The prefix to use when instantiating a new module"
},
"systemverilog.condenseBlankLines": {
"type":"boolean",
"default": false,
"description": "When aligning code leave blank lines between lines"
},
"systemverilog.alignEndOfLine": {
"type": "boolean",
"default": false,
"description": "Align the comma at the end of the port definition"
}
}
},
"commands": [
{
"command": "extension.systemverilog.instantiateModule",
"title": "System Verilog: Instantiate Module"
},
{
"command": "extension.systemverilog.alignment",
"title": "System Verilog: alignment"
}
],
"menus": {
"editor/context": [{
"command": "extension.systemverilog.alignment",
"when": "editorHasSelection",
"group": "1_modification"
}]
},
"keybindings": [{
"command": "extension.systemverilog.alignment",
"key": "alt+=",
"mac": "alt+=",
"when": "editorHasSelection"
}]
},
"activationEvents": [
"onLanguage:systemverilog"
],
"main": "./out/src/extension",
"scripts": {
"vscode:prepublish": "tsc -p ./",
"compile": "tsc -watch -p ./",
"postinstall": "node ./node_modules/vscode/bin/install"
},
"devDependencies": {
"typescript": "^2.0.3",
"vscode": "^1.0.0",
"@types/node": "*"
}
}