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lcd.c
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/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License as published by the Free Software Foundation;
* either version 2, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
* the implied warranty of MERCHANTABILITY or FITNESS FOR
* A PARTICULAR PURPOSE.See the GNU General Public License
* for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include "global.h"
#include "lcdtbl.h"
#include "via_hw.h"
static struct iga2_shadow_crtc_timing iga2_shadow_crtc_reg = {
/* IGA2 Shadow Horizontal Total */
{IGA2_SHADOW_HOR_TOTAL_REG_NUM, {{CR6D, 0, 7}, {CR71, 3, 3} } },
/* IGA2 Shadow Horizontal Blank End */
{IGA2_SHADOW_HOR_BLANK_END_REG_NUM, {{CR6E, 0, 7} } },
/* IGA2 Shadow Vertical Total */
{IGA2_SHADOW_VER_TOTAL_REG_NUM, {{CR6F, 0, 7}, {CR71, 0, 2} } },
/* IGA2 Shadow Vertical Addressable Video */
{IGA2_SHADOW_VER_ADDR_REG_NUM, {{CR70, 0, 7}, {CR71, 4, 6} } },
/* IGA2 Shadow Vertical Blank Start */
{IGA2_SHADOW_VER_BLANK_START_REG_NUM,
{{CR72, 0, 7}, {CR74, 4, 6} } },
/* IGA2 Shadow Vertical Blank End */
{IGA2_SHADOW_VER_BLANK_END_REG_NUM, {{CR73, 0, 7}, {CR74, 0, 2} } },
/* IGA2 Shadow Vertical Sync Start */
{IGA2_SHADOW_VER_SYNC_START_REG_NUM, {{CR75, 0, 7}, {CR76, 4, 6} } },
/* IGA2 Shadow Vertical Sync End */
{IGA2_SHADOW_VER_SYNC_END_REG_NUM, {{CR76, 0, 3} } }
};
static struct _lcd_scaling_factor lcd_scaling_factor = {
/* LCD Horizontal Scaling Factor Register */
{LCD_HOR_SCALING_FACTOR_REG_NUM,
{{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
/* LCD Vertical Scaling Factor Register */
{LCD_VER_SCALING_FACTOR_REG_NUM,
{{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
};
static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
/* LCD Horizontal Scaling Factor Register */
{LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
/* LCD Vertical Scaling Factor Register */
{LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
};
static struct
{
u32 res_id, xres, yres;
} lcd_panel_id2res[] =
{
{VIA_RES_640X480, 640, 480}, /* ID 0 */
{VIA_RES_800X600, 800, 600}, /* ID 1 */
{VIA_RES_1024X768, 1024, 768}, /* ID 2 */
{VIA_RES_1280X768, 1280, 768}, /* ID 3 */
{VIA_RES_1280X1024, 1280, 1024}, /* ID 4 */
{VIA_RES_1400X1050, 1400, 1050}, /* ID 5 */
{VIA_RES_1600X1200, 1600, 1200}, /* ID 6 */
{VIA_RES_1366X768, 1366, 768}, /* ID 7 */
{VIA_RES_1024X600, 1024, 600}, /* ID 8 */
{VIA_RES_1280X800, 1280, 800}, /* ID 9 */
{VIA_RES_800X480, 800, 480}, /* ID 10 */
{VIA_RES_1360X768, 1360, 768}, /* ID 11 */
{VIA_RES_480X640, 480, 640}, /* ID 12 */
{VIA_RES_1200X900, 1200, 900} /* ID 13 */
};
static struct
{
int lcd_panel_id, dualedge, dithering;
} flat_panel_id2info[] =
{
{LCD_PANEL_ID0_640X480, 0, 1}, /* ID = 0 */
{LCD_PANEL_ID1_800X600, 0, 1}, /* ID = 1 */
{LCD_PANEL_ID2_1024X768, 0, 1}, /* ID = 2 */
{LCD_PANEL_ID3_1280X768, 0, 1}, /* ID = 3 */
{LCD_PANEL_ID4_1280X1024, 1, 1}, /* ID = 4 */
{LCD_PANEL_ID5_1400X1050, 1, 1}, /* ID = 5 */
{LCD_PANEL_ID6_1600X1200, 1, 1}, /* ID = 6 */
{LCD_PANEL_ID1_800X600, 0, 1}, /* missing */
{LCD_PANEL_IDA_800X480, 0, 1}, /* ID = 8 */
{LCD_PANEL_ID2_1024X768, 1, 1}, /* ID = 9 */
{LCD_PANEL_ID2_1024X768, 0, 0}, /* ID = 10 */
{LCD_PANEL_ID2_1024X768, 1, 0}, /* ID = 11 */
{LCD_PANEL_ID3_1280X768, 0, 0}, /* ID = 12 */
{LCD_PANEL_ID4_1280X1024, 1, 0}, /* ID = 13 */
{LCD_PANEL_ID5_1400X1050, 1 ,0}, /* ID = 14 */
{LCD_PANEL_ID6_1600X1200, 1 ,0}, /* ID = 15 */
{LCD_PANEL_ID7_1366X768, 0, 0}, /* ID = 16 */
{LCD_PANEL_ID8_1024X600, 0, 1}, /* ID = 17 */
{LCD_PANEL_ID3_1280X768, 1, 1}, /* ID = 18 */
{LCD_PANEL_ID9_1280X800, 0, 1}, /* ID = 19 */
{LCD_PANEL_IDB_1360X768, 0, 0}, /* ID = 20 */
{LCD_PANEL_ID3_1280X768,1 , 0}, /* ID = 21 */
{LCD_PANEL_IDC_480X640, 0, 1}, /* ID = 22 */
{LCD_PANEL_IDD_1200X900, 0, 0} /* ID = 23 */
};
static int check_lvds_chip(int device_id_subaddr, int device_id);
static bool lvds_identify_integratedlvds(void);
static int lvds_register_read(int index);
static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
int panel_vres);
static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
int panel_id);
static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
int panel_id);
static void load_lcd_patch_regs(int set_hres, int set_vres,
int panel_id, int set_iga);
static void via_pitch_alignment_patch_lcd(
struct lvds_setting_information *plvds_setting_info,
struct lvds_chip_information
*plvds_chip_info);
static void lcd_patch_skew_dvp0(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info);
static void lcd_patch_skew_dvp1(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info);
static void lcd_patch_skew(struct lvds_setting_information
*plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
static void integrated_lvds_disable(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info);
static void integrated_lvds_enable(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info);
static void lcd_powersequence_off(void);
static void lcd_powersequence_on(void);
static void fill_lcd_format(void);
static void check_diport_of_integrated_lvds(
struct lvds_chip_information *plvds_chip_info,
struct lvds_setting_information
*plvds_setting_info);
static struct display_timing lcd_centering_timging(struct display_timing
mode_crt_reg,
struct display_timing panel_crt_reg);
static void load_crtc_shadow_timing(struct display_timing mode_timing,
struct display_timing panel_timing);
static void viafb_load_scaling_factor_for_p4m900(int set_hres,
int set_vres, int panel_hres, int panel_vres);
static int check_lvds_chip(int device_id_subaddr, int device_id)
{
if (lvds_register_read(device_id_subaddr) == device_id)
return OK;
else
return FAIL;
}
int viafb_lcd_get_support_expand_state( int xres, int yres )
{
return (viafb_lcd_panel_id < sizeof( lcd_panel_id2res ) / sizeof( lcd_panel_id2res[0] )
&& xres <= lcd_panel_id2res[viafb_lcd_panel_id].xres
&& yres <= lcd_panel_id2res[viafb_lcd_panel_id].yres);
}
void viafb_init_lcd_size(void)
{
struct lvds_setting_information *lvds_info = viaparinfo->lvds_setting_info,
*lvds_info2 = viaparinfo->lvds_setting_info2;
int index, method = viaparinfo->lvds_setting_info->get_lcd_size_method;
DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
DEBUG_MSG(KERN_INFO
"viaparinfo->lvds_setting_info->get_lcd_size_method %d\n",
lvds_info->get_lcd_size_method);
if (method != GET_LCD_SIZE_BY_SYSTEM_BIOS
&& method != GET_LCD_SZIE_BY_HW_STRAPPING)
{
if (method != GET_LCD_SIZE_BY_VGA_BIOS &&
method != GET_LCD_SIZE_BY_USER_SETTING)
viafb_lcd_panel_id = 1;
if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
viafb_lcd_panel_id = viafb_read_reg(VIACR, CR3F) & 0x0F;
if (viafb_lcd_panel_id > sizeof( flat_panel_id2info ) / sizeof( flat_panel_id2info[0] ))
viafb_lcd_panel_id = 1;
index = flat_panel_id2info[ viafb_lcd_panel_id ].lcd_panel_id;
lvds_info->lcd_panel_hres = lcd_panel_id2res[ index ].xres;
lvds_info->lcd_panel_vres = lcd_panel_id2res[ index ].yres;
lvds_info->lcd_panel_id = index;
lvds_info->device_lcd_dualedge = flat_panel_id2info[ viafb_lcd_panel_id ].dualedge;
lvds_info->LCDDithering = flat_panel_id2info[ viafb_lcd_panel_id ].dithering;
lvds_info->lcd_panel_size =lcd_panel_id2res[ index ].res_id;
}
lvds_info2->lcd_panel_id = lvds_info->lcd_panel_id;
lvds_info2->lcd_panel_size = lvds_info->lcd_panel_size;
lvds_info2->lcd_panel_hres = lvds_info->lcd_panel_hres;
lvds_info2->lcd_panel_vres = lvds_info->lcd_panel_vres;
lvds_info2->device_lcd_dualedge = lvds_info->device_lcd_dualedge;
lvds_info2->LCDDithering = lvds_info->LCDDithering;
}
static bool lvds_identify_integratedlvds(void)
{
if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
/* Two dual channel LCD (Internal LVDS + External LVDS): */
/* If we have an external LVDS, such as VT1636, we should
have its chip ID already. */
if (viaparinfo->chip_info->lvds.name) {
viaparinfo->chip_info->lvds2.name = INTEGRATED_LVDS;
DEBUG_MSG(KERN_INFO "Support two dual channel LVDS!\
(Internal LVDS + External LVDS)\n");
} else {
viaparinfo->chip_info->lvds.name = INTEGRATED_LVDS;
DEBUG_MSG(KERN_INFO "Not found external LVDS,\
so can't support two dual channel LVDS!\n");
}
} else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
/* Two single channel LCD (Internal LVDS + Internal LVDS): */
viaparinfo->chip_info->lvds.name = INTEGRATED_LVDS;
viaparinfo->chip_info->lvds2.name = INTEGRATED_LVDS;
DEBUG_MSG(KERN_INFO "Support two single channel LVDS!\
(Internal LVDS + Internal LVDS)\n");
} else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
/* If we have found external LVDS, just use it,
otherwise, we will use internal LVDS as default. */
if (!viaparinfo->chip_info->lvds.name) {
viaparinfo->chip_info->lvds.name = INTEGRATED_LVDS;
DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
}
} else {
viaparinfo->chip_info->lvds.name = NON_LVDS_TRANSMITTER;
DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
return false;
}
return true;
}
int viafb_lvds_trasmitter_identify(void)
{
viaparinfo->i2c_stuff.i2c_port = I2CPORTINDEX;
if (viafb_lvds_identify_vt1636()) {
viaparinfo->chip_info->lvds.i2c_port = I2CPORTINDEX;
DEBUG_MSG(KERN_INFO
"Found VIA VT1636 LVDS on port i2c 0x31 \n");
} else {
viaparinfo->i2c_stuff.i2c_port = GPIOPORTINDEX;
if (viafb_lvds_identify_vt1636()) {
viaparinfo->chip_info->lvds.i2c_port = GPIOPORTINDEX;
DEBUG_MSG(KERN_INFO
"Found VIA VT1636 LVDS on port gpio 0x2c \n");
}
}
if (viaparinfo->chip_info->name == UNICHROME_CX700)
lvds_identify_integratedlvds();
if (viaparinfo->chip_info->lvds.name)
return true;
/* Check for VT1631: */
viaparinfo->chip_info->lvds.name = VT1631_LVDS;
viaparinfo->chip_info->lvds.i2c_slave_addr = VT1631_LVDS_I2C_ADDR;
if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
DEBUG_MSG(KERN_INFO "\n %2d",
viaparinfo->chip_info->lvds.name);
DEBUG_MSG(KERN_INFO "\n %2d",
viaparinfo->chip_info->lvds.name);
return OK;
}
viaparinfo->chip_info->lvds.name = NON_LVDS_TRANSMITTER;
viaparinfo->chip_info->lvds.i2c_slave_addr = VT1631_LVDS_I2C_ADDR;
return FAIL;
}
static int lvds_register_read(int index)
{
u8 data;
viaparinfo->i2c_stuff.i2c_port = GPIOPORTINDEX;
viafb_i2c_readbyte((u8) viaparinfo->chip_info->lvds.i2c_slave_addr,
(u8) index, &data);
return data;
}
static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
int panel_vres)
{
int reg_value = 0;
int viafb_load_reg_num;
struct io_register *reg = NULL;
DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
/* LCD Scaling Enable */
viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
if (UNICHROME_P4M900 == viaparinfo->chip_info->name) {
viafb_load_scaling_factor_for_p4m900(set_hres, set_vres,
panel_hres, panel_vres);
return;
}
/* Check if expansion for horizontal */
if (set_hres != panel_hres) {
/* Load Horizontal Scaling Factor */
switch (viaparinfo->chip_info->name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
reg_value =
CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
viafb_load_reg_num =
lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
reg_num;
reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
viafb_load_reg(reg_value,
viafb_load_reg_num, reg, VIACR);
break;
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
case UNICHROME_CX700:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
reg_value =
K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
/* Horizontal scaling enabled */
viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
viafb_load_reg_num =
lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
viafb_load_reg(reg_value,
viafb_load_reg_num, reg, VIACR);
break;
}
DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
} else {
/* Horizontal scaling disabled */
viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
}
/* Check if expansion for vertical */
if (set_vres != panel_vres) {
/* Load Vertical Scaling Factor */
switch (viaparinfo->chip_info->name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
reg_value =
CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
viafb_load_reg_num =
lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
reg_num;
reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
viafb_load_reg(reg_value,
viafb_load_reg_num, reg, VIACR);
break;
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
case UNICHROME_CX700:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
reg_value =
K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
/* Vertical scaling enabled */
viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
viafb_load_reg_num =
lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
viafb_load_reg(reg_value,
viafb_load_reg_num, reg, VIACR);
break;
}
DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
} else {
/* Vertical scaling disabled */
viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
}
}
static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
int panel_id)
{
int vmode_index;
int reg_num = 0;
struct io_reg *lcd_patch_reg = NULL;
vmode_index = viafb_get_mode_index( set_hres, set_vres );
switch (panel_id) {
/* LCD 800x600 */
case LCD_PANEL_ID1_800X600:
switch (vmode_index) {
case VIA_RES_640X400:
case VIA_RES_640X480:
reg_num = NUM_TOTAL_K400_LCD_RES_6X4_8X6;
lcd_patch_reg = K400_LCD_RES_6X4_8X6;
break;
case VIA_RES_720X480:
case VIA_RES_720X576:
reg_num = NUM_TOTAL_K400_LCD_RES_7X4_8X6;
lcd_patch_reg = K400_LCD_RES_7X4_8X6;
break;
}
break;
/* LCD 1024x768 */
case LCD_PANEL_ID2_1024X768:
switch (vmode_index) {
case VIA_RES_640X400:
case VIA_RES_640X480:
reg_num = NUM_TOTAL_K400_LCD_RES_6X4_10X7;
lcd_patch_reg = K400_LCD_RES_6X4_10X7;
break;
case VIA_RES_720X480:
case VIA_RES_720X576:
reg_num = NUM_TOTAL_K400_LCD_RES_7X4_10X7;
lcd_patch_reg = K400_LCD_RES_7X4_10X7;
break;
case VIA_RES_800X600:
reg_num = NUM_TOTAL_K400_LCD_RES_8X6_10X7;
lcd_patch_reg = K400_LCD_RES_8X6_10X7;
break;
}
break;
/* LCD 1280x1024 */
case LCD_PANEL_ID4_1280X1024:
switch (vmode_index) {
case VIA_RES_640X400:
case VIA_RES_640X480:
reg_num = NUM_TOTAL_K400_LCD_RES_6X4_12X10;
lcd_patch_reg = K400_LCD_RES_6X4_12X10;
break;
case VIA_RES_720X480:
case VIA_RES_720X576:
reg_num = NUM_TOTAL_K400_LCD_RES_7X4_12X10;
lcd_patch_reg = K400_LCD_RES_7X4_12X10;
break;
case VIA_RES_800X600:
reg_num = NUM_TOTAL_K400_LCD_RES_8X6_12X10;
lcd_patch_reg = K400_LCD_RES_8X6_12X10;
break;
case VIA_RES_1024X768:
reg_num = NUM_TOTAL_K400_LCD_RES_10X7_12X10;
lcd_patch_reg = K400_LCD_RES_10X7_12X10;
break;
}
break;
/* LCD 1400x1050 */
case LCD_PANEL_ID5_1400X1050:
switch (vmode_index) {
case VIA_RES_640X480:
reg_num = NUM_TOTAL_K400_LCD_RES_6X4_14X10;
lcd_patch_reg = K400_LCD_RES_6X4_14X10;
break;
case VIA_RES_800X600:
reg_num = NUM_TOTAL_K400_LCD_RES_8X6_14X10;
lcd_patch_reg = K400_LCD_RES_8X6_14X10;
break;
case VIA_RES_1024X768:
reg_num = NUM_TOTAL_K400_LCD_RES_10X7_14X10;
lcd_patch_reg = K400_LCD_RES_10X7_14X10;
break;
case VIA_RES_1280X768:
case VIA_RES_1280X800:
case VIA_RES_1280X960:
case VIA_RES_1280X1024:
reg_num = NUM_TOTAL_K400_LCD_RES_12X10_14X10;
lcd_patch_reg = K400_LCD_RES_12X10_14X10;
break;
}
break;
/* LCD 1600x1200 */
case LCD_PANEL_ID6_1600X1200:
switch (vmode_index) {
case VIA_RES_640X400:
case VIA_RES_640X480:
reg_num = NUM_TOTAL_K400_LCD_RES_6X4_16X12;
lcd_patch_reg = K400_LCD_RES_6X4_16X12;
break;
case VIA_RES_720X480:
case VIA_RES_720X576:
reg_num = NUM_TOTAL_K400_LCD_RES_7X4_16X12;
lcd_patch_reg = K400_LCD_RES_7X4_16X12;
break;
case VIA_RES_800X600:
reg_num = NUM_TOTAL_K400_LCD_RES_8X6_16X12;
lcd_patch_reg = K400_LCD_RES_8X6_16X12;
break;
case VIA_RES_1024X768:
reg_num = NUM_TOTAL_K400_LCD_RES_10X7_16X12;
lcd_patch_reg = K400_LCD_RES_10X7_16X12;
break;
case VIA_RES_1280X768:
case VIA_RES_1280X800:
case VIA_RES_1280X960:
case VIA_RES_1280X1024:
reg_num = NUM_TOTAL_K400_LCD_RES_12X10_16X12;
lcd_patch_reg = K400_LCD_RES_12X10_16X12;
break;
}
break;
/* LCD 1366x768 */
case LCD_PANEL_ID7_1366X768:
switch (vmode_index) {
case VIA_RES_640X480:
reg_num = NUM_TOTAL_K400_LCD_RES_6X4_1366X7;
lcd_patch_reg = K400_LCD_RES_6X4_1366X7;
break;
case VIA_RES_720X480:
case VIA_RES_720X576:
reg_num = NUM_TOTAL_K400_LCD_RES_7X4_1366X7;
lcd_patch_reg = K400_LCD_RES_7X4_1366X7;
break;
case VIA_RES_800X600:
reg_num = NUM_TOTAL_K400_LCD_RES_8X6_1366X7;
lcd_patch_reg = K400_LCD_RES_8X6_1366X7;
break;
case VIA_RES_1024X768:
reg_num = NUM_TOTAL_K400_LCD_RES_10X7_1366X7;
lcd_patch_reg = K400_LCD_RES_10X7_1366X7;
break;
case VIA_RES_1280X768:
case VIA_RES_1280X800:
case VIA_RES_1280X960:
case VIA_RES_1280X1024:
reg_num = NUM_TOTAL_K400_LCD_RES_12X10_1366X7;
lcd_patch_reg = K400_LCD_RES_12X10_1366X7;
break;
}
break;
/* LCD 1360x768 */
case LCD_PANEL_IDB_1360X768:
break;
}
if (reg_num != 0) {
/* H.W. Reset : ON */
viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
viafb_write_regx(lcd_patch_reg, reg_num);
/* H.W. Reset : OFF */
viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
/* Reset PLL */
viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
/* Fire! */
outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
}
}
static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
int panel_id)
{
int vmode_index;
int reg_num = 0;
struct io_reg *lcd_patch_reg = NULL;
vmode_index = viafb_get_mode_index( set_hres, set_vres );
switch (panel_id) {
case LCD_PANEL_ID5_1400X1050:
switch (vmode_index) {
case VIA_RES_640X480:
reg_num = NUM_TOTAL_P880_LCD_RES_6X4_14X10;
lcd_patch_reg = P880_LCD_RES_6X4_14X10;
break;
case VIA_RES_800X600:
reg_num = NUM_TOTAL_P880_LCD_RES_8X6_14X10;
lcd_patch_reg = P880_LCD_RES_8X6_14X10;
break;
}
break;
case LCD_PANEL_ID6_1600X1200:
switch (vmode_index) {
case VIA_RES_640X400:
case VIA_RES_640X480:
reg_num = NUM_TOTAL_P880_LCD_RES_6X4_16X12;
lcd_patch_reg = P880_LCD_RES_6X4_16X12;
break;
case VIA_RES_720X480:
case VIA_RES_720X576:
reg_num = NUM_TOTAL_P880_LCD_RES_7X4_16X12;
lcd_patch_reg = P880_LCD_RES_7X4_16X12;
break;
case VIA_RES_800X600:
reg_num = NUM_TOTAL_P880_LCD_RES_8X6_16X12;
lcd_patch_reg = P880_LCD_RES_8X6_16X12;
break;
case VIA_RES_1024X768:
reg_num = NUM_TOTAL_P880_LCD_RES_10X7_16X12;
lcd_patch_reg = P880_LCD_RES_10X7_16X12;
break;
case VIA_RES_1280X768:
case VIA_RES_1280X960:
case VIA_RES_1280X1024:
reg_num = NUM_TOTAL_P880_LCD_RES_12X10_16X12;
lcd_patch_reg = P880_LCD_RES_12X10_16X12;
break;
}
break;
}
if (reg_num != 0) {
/* H.W. Reset : ON */
viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
viafb_write_regx(lcd_patch_reg, reg_num);
/* H.W. Reset : OFF */
viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
/* Reset PLL */
viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
/* Fire! */
outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
}
}
static void load_lcd_patch_regs(int set_hres, int set_vres,
int panel_id, int set_iga)
{
int vmode_index;
vmode_index = viafb_get_mode_index( set_hres, set_vres );
viafb_unlock_crt();
/* Patch for simultaneous & Expansion */
if ((set_iga == IGA1_IGA2) &&
(viaparinfo->lvds_setting_info->display_method ==
LCD_EXPANDSION)) {
switch (viaparinfo->chip_info->name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
load_lcd_k400_patch_tbl(set_hres, set_vres, panel_id);
break;
case UNICHROME_K800:
break;
case UNICHROME_PM800:
case UNICHROME_CN700:
case UNICHROME_CX700:
load_lcd_p880_patch_tbl(set_hres, set_vres, panel_id);
}
}
viafb_lock_crt();
}
static void via_pitch_alignment_patch_lcd(
struct lvds_setting_information *plvds_setting_info,
struct lvds_chip_information
*plvds_chip_info)
{
unsigned char cr13, cr35, cr65, cr66, cr67;
unsigned long dwScreenPitch = 0;
unsigned long dwPitch;
dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
if (dwPitch & 0x1F) {
dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
if (plvds_setting_info->iga_path == IGA2) {
if (plvds_setting_info->bpp > 8) {
cr66 = (unsigned char)(dwScreenPitch & 0xFF);
viafb_write_reg(CR66, VIACR, cr66);
cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
cr67 |=
(unsigned
char)((dwScreenPitch & 0x300) >> 8);
viafb_write_reg(CR67, VIACR, cr67);
}
/* Fetch Count */
cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
viafb_write_reg(CR67, VIACR, cr67);
cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
cr65 += 2;
viafb_write_reg(CR65, VIACR, cr65);
} else {
if (plvds_setting_info->bpp > 8) {
cr13 = (unsigned char)(dwScreenPitch & 0xFF);
viafb_write_reg(CR13, VIACR, cr13);
cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
cr35 |=
(unsigned
char)((dwScreenPitch & 0x700) >> 3);
viafb_write_reg(CR35, VIACR, cr35);
}
}
}
}
static void lcd_patch_skew_dvp0(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
if (VT1636_LVDS == plvds_chip_info->name) {
switch (viaparinfo->chip_info->name) {
case UNICHROME_P4M900:
viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
plvds_chip_info);
break;
case UNICHROME_P4M890:
viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
plvds_chip_info);
break;
}
}
}
static void lcd_patch_skew_dvp1(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
if (VT1636_LVDS == plvds_chip_info->name) {
switch (viaparinfo->chip_info->name) {
case UNICHROME_CX700:
viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
plvds_chip_info);
break;
}
}
}
static void lcd_patch_skew(struct lvds_setting_information
*plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
{
DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
switch (plvds_chip_info->output_interface) {
case INTERFACE_DVP0:
lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
break;
case INTERFACE_DVP1:
lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
break;
case INTERFACE_DFP_LOW:
if (UNICHROME_P4M900 == viaparinfo->chip_info->name) {
viafb_write_reg_mask(CR99, VIACR, 0x08,
BIT0 + BIT1 + BIT2 + BIT3);
}
break;
}
}
/* LCD Set Mode */
void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
struct lvds_setting_information *plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
int video_index = plvds_setting_info->lcd_panel_size;
int set_iga = plvds_setting_info->iga_path;
int mode_bpp = plvds_setting_info->bpp;
int set_hres, set_vres;
int panel_hres, panel_vres;
u32 pll_D_N;
int offset;
struct display_timing mode_crt_reg, panel_crt_reg;
struct crt_mode_table *panel_crt_table = NULL;
struct VideoModeTable *vmode_tbl = NULL;
struct display_timing crt_reg;
DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
/* Get mode table */
mode_crt_reg = mode_crt_table->crtc;
/* Get panel table Pointer */
vmode_tbl = viafb_get_modetbl_pointer(video_index);
panel_crt_table = vmode_tbl->crtc;
panel_crt_reg = panel_crt_table->crtc;
DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
set_hres = plvds_setting_info->h_active;
set_vres = plvds_setting_info->v_active;
panel_hres = plvds_setting_info->lcd_panel_hres;
panel_vres = plvds_setting_info->lcd_panel_vres;
if (VT1636_LVDS == plvds_chip_info->name)
viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
plvds_setting_info->vclk = panel_crt_table->clk;
if (set_iga == IGA1) {
/* IGA1 doesn't have LCD scaling, so set it as centering. */
crt_reg = lcd_centering_timging(mode_crt_reg, panel_crt_reg);
viafb_SetPrimaryDisplayTiming(
crt_reg.hor_addr,
crt_reg.ver_addr,
crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end),
crt_reg.hor_sync_start - crt_reg.hor_addr,
crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end),
crt_reg.ver_sync_start - crt_reg.ver_addr,
crt_reg.hor_sync_end,
crt_reg.ver_sync_end );
} else {
/* Expansion */
if ((plvds_setting_info->display_method ==
LCD_EXPANDSION) & ((set_hres != panel_hres)
|| (set_vres != panel_vres))) {
/* expansion timing IGA2 loaded panel set timing*/
crt_reg = panel_crt_reg;
load_lcd_scaling(set_hres, set_vres, panel_hres,
panel_vres);
DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
} else { /* Centering */
/* centering timing IGA2 always loaded panel
and mode releative timing */
crt_reg = lcd_centering_timging(mode_crt_reg, panel_crt_reg);
viafb_write_reg_mask(CR79, VIACR, 0x00,
BIT0 + BIT1 + BIT2);
/* LCD scaling disabled */
}
viafb_SetSecondaryDisplayTiming(
crt_reg.hor_addr,
crt_reg.ver_addr,
crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end),
crt_reg.hor_sync_start - crt_reg.hor_addr,
crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end),
crt_reg.ver_sync_start - crt_reg.ver_addr,
crt_reg.hor_sync_end,
crt_reg.ver_sync_end );
}
if (set_iga == IGA1_IGA2) {
load_crtc_shadow_timing(mode_crt_reg, panel_crt_reg);
/* Fill shadow registers */
switch (plvds_setting_info->lcd_panel_id) {
case LCD_PANEL_ID0_640X480:
offset = 80;
break;
case LCD_PANEL_ID1_800X600:
case LCD_PANEL_IDA_800X480:
offset = 110;
break;
case LCD_PANEL_ID2_1024X768:
offset = 150;
break;
case LCD_PANEL_ID3_1280X768:
case LCD_PANEL_ID4_1280X1024:
case LCD_PANEL_ID5_1400X1050:
case LCD_PANEL_ID9_1280X800:
offset = 190;
break;
case LCD_PANEL_ID6_1600X1200:
offset = 250;
break;
case LCD_PANEL_ID7_1366X768:
case LCD_PANEL_IDB_1360X768:
offset = 212;
break;
default:
offset = 140;
break;
}
/* Offset for simultaneous */
viafb_SetSecondaryDisplayLine( offset<<3 );
DEBUG_MSG(KERN_INFO "viafb_load_reg!!\n");
viafb_load_fetch_count_reg(set_hres, 4, IGA2);
/* Fetch count for simultaneous */
} else { /* SAMM */
/* Offset for IGA2 only */
if (set_iga == IGA1)
viafb_SetPrimaryDisplayLine( set_hres * mode_bpp / 8 );
else /* IGA2 */
viafb_SetSecondaryDisplayLine( set_hres * mode_bpp / 8 );
/* Fetch count for IGA2 only */
viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
if ((viaparinfo->chip_info->name != UNICHROME_CLE266)
&& (viaparinfo->chip_info->name != UNICHROME_K400))
viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
if (set_iga == IGA1)
viafb_SetPrimaryDisplayColor( mode_bpp );
else
viafb_SetSecondaryDisplayColor( mode_bpp );
}
fill_lcd_format();
pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
viafb_set_vclock(pll_D_N, set_iga);
viafb_set_output_path(DEVICE_LCD, set_iga,
plvds_chip_info->output_interface);
lcd_patch_skew(plvds_setting_info, plvds_chip_info);
/* If K8M800, enable LCD Prefetch Mode. */
if ((viaparinfo->chip_info->name == UNICHROME_K800)
|| (UNICHROME_K8M890 == viaparinfo->chip_info->name))
viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
load_lcd_patch_regs(set_hres, set_vres,
plvds_setting_info->lcd_panel_id, set_iga);
DEBUG_MSG(KERN_INFO "load_lcd_patch_regs!!\n");
/* Patch for non 32bit alignment mode */
via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
}
static void integrated_lvds_disable(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
bool turn_off_first_powersequence = false;
bool turn_off_second_powersequence = false;
if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
turn_off_first_powersequence = true;
if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
turn_off_first_powersequence = true;
if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
turn_off_second_powersequence = true;
if (turn_off_second_powersequence) {
/* Use second power sequence control: */
/* Turn off power sequence. */
viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
/* Turn off back light. */
viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
}
if (turn_off_first_powersequence) {
/* Use first power sequence control: */
/* Turn off power sequence. */
viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
/* Turn off back light. */
viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
}
/* Turn DFP High/Low Pad off. */
viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
/* Power off LVDS channel. */
switch (plvds_chip_info->output_interface) {
case INTERFACE_LVDS0:
viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
break;
case INTERFACE_LVDS1:
viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
break;
case INTERFACE_LVDS0LVDS1:
viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
break;
}
}
static void integrated_lvds_enable(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
plvds_chip_info->output_interface);
if (plvds_setting_info->lcd_mode == LCD_SPWG)
viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
else
viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
switch (plvds_chip_info->output_interface) {
case INTERFACE_LVDS0LVDS1:
case INTERFACE_LVDS0:
/* Use first power sequence control: */
/* Use hardware control power sequence. */
viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
/* Turn on back light. */
viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
/* Turn on hardware power sequence. */
viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
break;
case INTERFACE_LVDS1:
/* Use second power sequence control: */
/* Use hardware control power sequence. */
viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
/* Turn on back light. */
viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);