Bank_12_14_35.Harness

CDR_PLL_CTRL=CLK_SEL,Helper_DCXO_OE,Helper_DCXO_SCL,Helper_DCXO_SDA,Main_DCXO_OE,Main_DCXO_SCL,Main_DCXO_SDA
FPGA_TESTPOINT=FPGA_TESTPOINT0,FPGA_TESTPOINT1,FPGA_TESTPOINT2,FPGA_TESTPOINT3
SLOT=LVDS_0_P,LVDS_0_N,LVDS_1_P,LVDS_1_N,LVDS_2_P,LVDS_2_N,LVDS_3_P,LVDS_3_N,LVDS_4_P,LVDS_4_N,LVDS_5_P,LVDS_5_N,LVDS_6_P,LVDS_6_N,LVDS_7_P,LVDS_7_N,LVDS_8_P,LVDS_8_N,LVDS_9_P,LVDS_9_N,LVDS_10_P,LVDS_10_N,LVDS_11_P,LVDS_11_N,LVDS_12_P,LVDS_12_N,LVDS_13_P,LVDS_13_N,LVDS_14_P,LVDS_14_N,LVDS_15_P,LVDS_15_N