SoC_FPGA_HD_84_87.Harness

ARTIX_CFG=ARTIX_CFG_INIT_B,ARTIX_CFG_PROG_B,ARTIX_CFG_DIN,ARTIX_CFG_DONE,ARTIX_CFG_CCLK
MLVDS_DE=MLVDS_DE_1,MLVDS_DE_2,MLVDS_DE_3,MLVDS_DE_4,MLVDS_DE_5,MLVDS_DE_6,MLVDS_DE_7,MLVDS_DE_8,MLVDS_RE
MLVDS-FPGA=MLVDS_O_1,MLVDS_O_2,MLVDS_O_3,MLVDS_O_4,MLVDS_O_5,MLVDS_O_6,MLVDS_O_7,MLVDS_O_8,MLVDS_I_1,MLVDS_I_2,MLVDS_I_3,MLVDS_I_4,MLVDS_I_5,MLVDS_I_6,MLVDS_I_7,MLVDS_I_8
SI5341B_CTRL=IN_SEL[0..1],RST
UART=RxD,TxD