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mt9m114.c
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/*
* A V4L2 driver for Aptina MT9M114 cameras.
*
* Copyright 2011 Aldebaran Robotics Written
* by Joseph Pinkasfeld with substantial inspiration from ov7670 code.
*
* Authors:
* joseph pinkasfeld <joseph.pinkasfeld@gmail.com>
* Ludovic SMAL <lsmal@aldebaran-robotics.com>
* Corentin Le Molgat <clemolgat@aldebaran-robotics.com>
* Arne Böckmann <arneboe@tzi.de>
*
* This file may be distributed under the terms of the GNU General
* Public License, version 2.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <media/v4l2-device.h>
#include <media/v4l2-chip-ident.h>
#include <media/v4l2-i2c-drv.h>
MODULE_AUTHOR("Joseph Pinkasfeld <joseph.pinkasfeld@gmail.com>;Ludovic SMAL <lsmal@aldebaran-robotics.com>, Corentin Le Molgat <clemolgat@aldebaran-robotics.com>, Arne Böckmann <arneboe@tzi.de>");
MODULE_DESCRIPTION("A low-level driver for Aptina MT9M114 sensors");
MODULE_LICENSE("GPL");
static int debug = 0;
module_param(debug, bool, 0644);
MODULE_PARM_DESC(debug, "Debug level (0-1)");
#define dprintk(level, name, fmt, arg...)\
do { \
printk(KERN_DEBUG "%s/0: " fmt, name, ## arg);\
} while (0)
/*
* Basic window sizes. These probably belong somewhere more globally
* useful.
*/
#define WXGA_WIDTH 1280
#define WXGA_HEIGHT 720
#define FULL_HEIGHT 960
#define VGA_WIDTH 640
#define VGA_HEIGHT 480
#define QVGA_WIDTH 320
#define QVGA_HEIGHT 240
#define CIF_WIDTH 352
#define CIF_HEIGHT 288
#define QCIF_WIDTH 176
#define QCIF_HEIGHT 144
/*
* Our nominal (default) frame rate.
*/
#define MT9M114_FRAME_RATE 256
/*
* The MT9M114 sits on i2c with ID 0x48 or 0x5D
* depends on input SADDR
*/
#define MT9M114_I2C_ADDR 0x48
/* Registers */
#define REG_CHIP_ID 0x0000
#define REG_MON_MAJOR_VERSION 0x8000
#define REG_MON_MINOR_VERION 0x8002
#define REG_MON_RELEASE_VERSION 0x8004
#define REG_RESET_AND_MISC_CONTROL 0x001A
#define REG_PAD_SLEW_CONTROL 0x001E
#define REG_COMMAND_REGISTER 0x0080
#define HOST_COMMAND_APPLY_PATCH 0x0001
#define HOST_COMMAND_SET_STATE 0x0002
#define HOST_COMMAND_REFRESH 0x0004
#define HOST_COMMAND_WAIT_FOR_EVENT 0x0008
#define HOST_COMMAND_OK 0x8000
#define REG_ACCESS_CTL_STAT 0x0982
#define REG_PHYSICAL_ADDRESS_ACCESS 0x098A
#define REG_LOGICAL_ADDRESS_ACCESS 0x098E
#define MCU_VARIABLE_DATA0 0x0990
#define MCU_VARIABLE_DATA1 0x0992
#define REG_RESET_REGISTER 0x301A
#define REG_DAC_TXLO_ROW 0x316A
#define REG_DAC_TXLO 0x316C
#define REG_DAC_LD_4_5 0x3ED0
#define REG_DAC_LD_6_7 0x3ED2
#define REG_DAC_ECL 0x316E
#define REG_DELTA_DK_CONTROL 0x3180
#define REG_SAMP_COL_PUP2 0x3E14
#define REG_COLUMN_CORRECTION 0x30D4
#define REG_LL_ALGO 0xBC04
#define LL_EXEC_DELTA_DK_CORRECTION 0x0200
#define REG_CAM_DGAIN_RED 0xC840
#define REG_CAM_DGAIN_GREEN_1 0xC842
#define REG_CAM_DGAIN_GREEN_2 0xC844
#define REG_CAM_DGAIN_BLUE 0xC846
#define REG_CAM_SYSCTL_PLL_ENABLE 0xC97E
#define REG_CAM_SYSCTL_PLL_DIVIDER_M_N 0xC980
#define REG_CAM_SYSCTL_PLL_DIVIDER_P 0xC982
#define REG_CAM_SENSOR_CFG_Y_ADDR_START 0xC800
#define REG_CAM_SENSOR_CFG_X_ADDR_START 0xC802
#define REG_CAM_SENSOR_CFG_Y_ADDR_END 0xC804
#define REG_CAM_SENSOR_CFG_X_ADDR_END 0xC806
#define REG_CAM_SENSOR_CFG_PIXCLK 0xC808
#define REG_CAM_SENSOR_CFG_ROW_SPEED 0xC80C
#define REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN 0xC80E
#define REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX 0xC810
#define REG_CAM_SENSOR_CFG_FRAME_LENGTH_LINES 0xC812
#define REG_CAM_SENSOR_CFG_LINE_LENGTH_PCK 0xC814
#define REG_CAM_SENSOR_CFG_FINE_CORRECTION 0xC816
#define REG_CAM_SENSOR_CFG_CPIPE_LAST_ROW 0xC818
#define REG_CAM_SENSOR_CFG_REG_0_DATA 0xC826
#define REG_CAM_SENSOR_CONTROL_READ_MODE 0xC834
#define CAM_SENSOR_CONTROL_VERT_FLIP_EN 0x0002
#define CAM_SENSOR_CONTROL_HORZ_FLIP_EN 0x0001
#define CAM_SENSOR_CONTROL_BINNING_EN 0x0330
#define CAM_SENSOR_CONTROL_SKIPPING_EN 0x0110
#define CAM_MON_HEARTBEAT 0x8006 //the frame counter. updates on vertical blanking.
#define REG_CAM_CROP_WINDOW_XOFFSET 0xC854
#define REG_CAM_CROP_WINDOW_YOFFSET 0xC856
#define REG_CAM_CROP_WINDOW_WIDTH 0xC858
#define REG_CAM_CROP_WINDOW_HEIGHT 0xC85A
#define REG_CAM_CROP_CROPMODE 0xC85C
#define REG_CAM_OUTPUT_WIDTH 0xC868
#define REG_CAM_OUTPUT_HEIGHT 0xC86A
#define REG_CAM_OUTPUT_FORMAT 0xC86C
#define REG_CAM_OUTPUT_OFFSET 0xC870
#define REG_CAM_PORT_OUTPUT_CONTROL 0xC984
#define REG_CAM_OUPUT_FORMAT_YUV 0xC86E
#define REG_CAM_STAT_AWB_CLIP_WINDOW_XSTART 0xC914
#define REG_CAM_STAT_AWB_CLIP_WINDOW_YSTART 0xC916
#define REG_CAM_STAT_AWB_CLIP_WINDOW_XEND 0xC918
#define REG_CAM_STAT_AWB_CLIP_WINDOW_YEND 0xC91A
#define REG_CAM_STAT_AE_INITIAL_WINDOW_XSTART 0xC91C
#define REG_CAM_STAT_AE_INITIAL_WINDOW_YSTART 0xC91E
#define REG_CAM_STAT_AE_INITIAL_WINDOW_XEND 0xC920
#define REG_CAM_STAT_AE_INITIAL_WINDOW_YEND 0xC922
#define REG_CAM_PGA_PGA_CONTROL 0xC95E
#define REG_SYSMGR_NEXT_STATE 0xDC00
#define REG_SYSMGR_CURRENT_STATE 0xDC01
#define REG_PATCHLDR_LOADER_ADDRESS 0xE000
#define REG_PATCHLDR_PATCH_ID 0xE002
#define REG_PATCHLDR_FIRMWARE_ID 0xE004
#define REG_PATCHLDR_APPLY_STATUS 0xE008
#define REG_AUTO_BINNING_MODE 0xE801
#define REG_CAM_SENSOR_CFG_MAX_ANALOG_GAIN 0xC81C
#define REG_CROP_CROPMODE 0xC85C
#define REG_CAM_AET_AEMODE 0xC878
#define REG_CAM_AET_TARGET_AVG_LUMA 0xC87A
#define REG_CAM_AET_TARGET_AVERAGE_LUMA_DARK 0xC87B
#define REG_CAM_AET_BLACK_CLIPPING_TARGET 0xC87C
#define REG_CAM_AET_AE_MAX_VIRT_AGAIN 0xC886
#define REG_CAM_AET_MAX_FRAME_RATE 0xC88C
#define REG_CAM_AET_MIN_FRAME_RATE 0xC88E
#define REG_CAM_AET_TARGET_GAIN 0xC890
#define REG_AE_ALGORITHM 0xA404
#define REG_AE_TRACK_MODE 0xA802
#define REG_AE_TRACK_AE_TRACKING_DAMPENING_SPEED 0xA80A
#define REG_CAM_LL_START_BRIGHTNESS 0xC926
#define REG_CAM_LL_STOP_BRIGHTNESS 0xC928
#define REG_CAM_LL_START_GAIN_METRIC 0xC946
#define REG_CAM_LL_STOP_GAIN_METRIC 0xC948
#define REG_CAM_LL_START_TARGET_LUMA_BM 0xC952
#define REG_CAM_LL_STOP_TARGET_LUMA_BM 0xC954
#define REG_CAM_LL_START_SATURATION 0xC92A
#define REG_CAM_LL_END_SATURATION 0xC92B
#define REG_CAM_LL_START_DESATURATION 0xC92C
#define REG_CAM_LL_END_DESATURATION 0xC92D
#define REG_CAM_LL_START_DEMOSAIC 0xC92E
#define REG_CAM_LL_START_AP_GAIN 0xC92F
#define REG_CAM_LL_START_AP_THRESH 0xC930
#define REG_CAM_LL_STOP_DEMOSAIC 0xC931
#define REG_CAM_LL_STOP_AP_GAIN 0xC932
#define REG_CAM_LL_STOP_AP_THRESH 0xC933
#define REG_CAM_LL_START_NR_RED 0xC934
#define REG_CAM_LL_START_NR_GREEN 0xC935
#define REG_CAM_LL_START_NR_BLUE 0xC936
#define REG_CAM_LL_START_NR_THRESH 0xC937
#define REG_CAM_LL_STOP_NR_RED 0xC938
#define REG_CAM_LL_STOP_NR_GREEN 0xC939
#define REG_CAM_LL_STOP_NR_BLUE 0xC93A
#define REG_CAM_LL_STOP_NR_THRESH 0xC93B
#define REG_CAM_LL_START_CONTRAST_BM 0xC93C
#define REG_CAM_LL_STOP_CONTRAST_BM 0xC93E
#define REG_CAM_LL_GAMMA 0xC940
#define REG_CAM_LL_START_CONTRAST_GRADIENT 0xC942
#define REG_CAM_LL_STOP_CONTRAST_GRADIENT 0xC943
#define REG_CAM_LL_START_CONTRAST_LUMA_PERCENTAGE 0xC944
#define REG_CAM_LL_STOP_CONTRAST_LUMA_PERCENTAGE 0xC945
#define REG_CAM_LL_START_FADE_TO_BLACK_LUMA 0xC94A
#define REG_CAM_LL_STOP_FADE_TO_BLACK_LUMA 0xC94C
#define REG_CAM_LL_CLUSTER_DC_TH_BM 0xC94E
#define REG_CAM_LL_CLUSTER_DC_GATE_PERCENTAGE 0xC950
#define REG_CAM_LL_SUMMING_SENSITIVITY_FACTOR 0xC951
#define REG_CAM_LL_MODE 0xBC02 //might be BC07.
#define REG_CCM_DELTA_GAIN 0xB42A
#define REG_CAM_HUE_ANGLE 0xC873
// AWB
#define REG_AWB_AWB_MODE 0xC909
#define REG_AWB_COL_TEMP 0xC8F0//color temp, only writeable if awb mode is manual. in kelvin
#define REG_AWB_COL_TEMP_MAX 0xC8EE//maximum color temp in kelvin
#define REG_AWB_COL_TEMP_MIN 0xC8EC//minimum color temp in kelvin
// UVC
#define REG_UVC_AE_MODE 0xCC00
#define REG_UVC_AUTO_WHITE_BALANCE_TEMPERATURE 0xCC01
#define REG_UVC_AE_PRIORITY 0xCC02
#define REG_UVC_POWER_LINE_FREQUENCY 0xCC03
#define REG_UVC_EXPOSURE_TIME 0xCC04
#define REG_UVC_BACKLIGHT_COMPENSATION 0xCC08
#define REG_UVC_BRIGHTNESS 0xCC0A //set brightness in auto exposure mode.
#define REG_UVC_CONTRAST 0xCC0C //not exactly what the name suggests. See chip documentation
#define REG_UVC_GAIN 0xCC0E
#define REG_UVC_HUE 0xCC10
#define REG_UVC_SATURATION 0xCC12
#define REG_UVC_SHARPNESS 0xCC14
#define REG_UVC_GAMMA 0xCC16
#define REG_UVC_WHITE_BALANCE_TEMPERATURE 0xCC18
#define REG_UVC_FRAME_INTERVAL 0xCC1C
#define REG_UVC_MANUAL_EXPOSURE 0xCC20
#define REG_UVC_FLICKER_AVOIDANCE 0xCC21
#define REG_UVC_ALGO 0xCC22
#define REG_UVC_RESULT_STATUS 0xCC24
/**This variable selects the system event that the host wishes to wait for.
* 1: end of frame
* 2: start of frame */
#define REG_CMD_HANDLER_WAIT_FOR_EVENT 0xFC00
/** This variable determines the number of system event occurrences for which the
* Command Handler component will wait */
#define REG_CMD_HANDLER_NUM_WAIT_EVENTS 0xFC02
/**Result status code for last refresh command. Updates after refresh command.
* Possible values:
0x00: ENOERR - refresh successful
0x13: EINVCROPX - invalid horizontal crop configuration
0x14: EINVCROPY - invalid vertical crop configuration
0x15: EINVTC - invalid Tilt Correction percentage
*/
#define REG_SEQ_ERROR_CODE 0x8406
/* SYS_STATE values (for SYSMGR_NEXT_STATE and SYSMGR_CURRENT_STATE) */
#define MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE 0x28
#define MT9M114_SYS_STATE_STREAMING 0x31
#define MT9M114_SYS_STATE_START_STREAMING 0x34
#define MT9M114_SYS_STATE_ENTER_SUSPEND 0x40
#define MT9M114_SYS_STATE_SUSPENDED 0x41
#define MT9M114_SYS_STATE_ENTER_STANDBY 0x50
#define MT9M114_SYS_STATE_STANDBY 0x52
#define MT9M114_SYS_STATE_LEAVE_STANDBY 0x54
//Custom V4L control variables
#define V4L2_MT9M114_FADE_TO_BLACK (V4L2_CID_PRIVATE_BASE) //boolean, enable or disable fade to black feature
/**
* This enum is used as index for the state's uvc_register_out_of_sync array.
*/
typedef enum {
UVC_EXPOSURE_TIME,
UVC_GAIN,
UVC_BRIGHTNESS,
UVC_CONTRAST,
UVC_SATURATION,
UVC_SHARPNESS,
NUM_OF_UVC_REGISTERS /** < This value should always be the last! */
} uvc_registers;
/*
* Information we maintain about a known sensor.
*/
struct mt9m114_format_struct; /* coming later */
struct mt9m114_info {
struct v4l2_subdev sd;
struct mt9m114_format_struct *fmt; /* Current format */
unsigned char sat; /* Saturation value */
int hue; /* Hue value */
int flag_vflip; /* flip vertical */
int flag_hflip; /* flip horizontal */
/* The change config command sometimes breaks the sync between uvc registers and cam
* variables. This array keeps track of which uvc registers are out of sync
* and which are not. Use the uvc_registers enum to access this array */
bool uvc_register_out_of_sync[NUM_OF_UVC_REGISTERS];
};
static inline struct mt9m114_info *to_state(struct v4l2_subdev *sd)
{
return container_of(sd, struct mt9m114_info, sd);
}
/*
* The default register settings. There
* is really no making sense of most of these - lots of "reserved" values
* and such.
* FIXME this might be a leftover from the old omnivision driver?!
* These settings give VGA YUYV.
*/
struct regval_list {
u16 reg_num;
u16 size;
u32 value;
};
static struct regval_list pga_regs[] = {
{ 0x098E, 2, 0},
{ 0xC95E, 2, 3},
{ 0xC95E, 2, 2},
{ 0x3640, 2, 368},
{ 0x3642, 2, 3787},
{ 0x3644, 2, 22480},
{ 0x3646, 2, 33549},
{ 0x3648, 2, 62062},
{ 0x364A, 2, 32303},
{ 0x364C, 2, 18603},
{ 0x364E, 2, 26192},
{ 0x3650, 2, 52556},
{ 0x3652, 2, 44686},
{ 0x3654, 2, 32431},
{ 0x3656, 2, 23244},
{ 0x3658, 2, 7056},
{ 0x365A, 2, 64140},
{ 0x365C, 2, 37614},
{ 0x365E, 2, 32207},
{ 0x3660, 2, 19178},
{ 0x3662, 2, 26800},
{ 0x3664, 2, 45101},
{ 0x3666, 2, 43151},
{ 0x3680, 2, 13964},
{ 0x3682, 2, 1869},
{ 0x3684, 2, 9871},
{ 0x3686, 2, 32394},
{ 0x3688, 2, 38832},
{ 0x368A, 2, 492},
{ 0x368C, 2, 2894},
{ 0x368E, 2, 4687},
{ 0x3690, 2, 45006},
{ 0x3692, 2, 34192},
{ 0x3694, 2, 973},
{ 0x3696, 2, 2349},
{ 0x3698, 2, 25323},
{ 0x369A, 2, 41294},
{ 0x369C, 2, 46959},
{ 0x369E, 2, 3405},
{ 0x36A0, 2, 47531},
{ 0x36A2, 2, 38860},
{ 0x36A4, 2, 22506},
{ 0x36A6, 2, 37359},
{ 0x36C0, 2, 3569},
{ 0x36C2, 2, 36620},
{ 0x36C4, 2, 30224},
{ 0x36C6, 2, 11116},
{ 0x36C8, 2, 42739},
{ 0x36CA, 2, 1681},
{ 0x36CC, 2, 61514},
{ 0x36CE, 2, 13265},
{ 0x36D0, 2, 44462},
{ 0x36D2, 2, 51635},
{ 0x36D4, 2, 23184},
{ 0x36D6, 2, 39789},
{ 0x36D8, 2, 22480},
{ 0x36DA, 2, 3885},
{ 0x36DC, 2, 64882},
{ 0x36DE, 2, 3505},
{ 0x36E0, 2, 46314},
{ 0x36E2, 2, 26864},
{ 0x36E4, 2, 36813},
{ 0x36E6, 2, 41555},
{ 0x3700, 2, 1325},
{ 0x3702, 2, 60557},
{ 0x3704, 2, 46961},
{ 0x3706, 2, 13199},
{ 0x3708, 2, 25234},
{ 0x370A, 2, 10253},
{ 0x370C, 2, 36912},
{ 0x370E, 2, 46449},
{ 0x3710, 2, 17713},
{ 0x3712, 2, 19282},
{ 0x3714, 2, 10509},
{ 0x3716, 2, 53295},
{ 0x3718, 2, 38417},
{ 0x371A, 2, 8881},
{ 0x371C, 2, 26834},
{ 0x371E, 2, 27981},
{ 0x3720, 2, 39469},
{ 0x3722, 2, 34321},
{ 0x3724, 2, 5232},
{ 0x3726, 2, 20978},
{ 0x3740, 2, 35307},
{ 0x3742, 2, 49806},
{ 0x3744, 2, 62036},
{ 0x3746, 2, 23250},
{ 0x3748, 2, 27830},
{ 0x374A, 2, 8111},
{ 0x374C, 2, 51085},
{ 0x374E, 2, 33653},
{ 0x3750, 2, 24914},
{ 0x3752, 2, 29270},
{ 0x3754, 2, 5133},
{ 0x3756, 2, 5933},
{ 0x3758, 2, 52436},
{ 0x375A, 2, 13362},
{ 0x375C, 2, 18166},
{ 0x375E, 2, 37550},
{ 0x3760, 2, 39566},
{ 0x3762, 2, 61300},
{ 0x3764, 2, 23602},
{ 0x3766, 2, 26198},
{ 0x3782, 2, 480},
{ 0x3784, 2, 672},
{ 0xC960, 2, 2800},
{ 0xC962, 2, 31149},
{ 0xC964, 2, 22448},
{ 0xC966, 2, 30936},
{ 0xC968, 2, 29792},
{ 0xC96A, 2, 4000},
{ 0xC96C, 2, 33143},
{ 0xC96E, 2, 33116},
{ 0xC970, 2, 33041},
{ 0xC972, 2, 32855},
{ 0xC974, 2, 6500},
{ 0xC976, 2, 31786},
{ 0xC978, 2, 26268},
{ 0xC97A, 2, 32319},
{ 0xC97C, 2, 29650},
{ 0xC95E, 2, 3},
{ 0xffff, 0xffff ,0xffff}
};
static struct regval_list ccm_awb_regs[] = {
{ 0xC892, 2, 615},
{ 0xC894, 2, 65306},
{ 0xC896, 2, 65459},
{ 0xC898, 2, 65408},
{ 0xC89A, 2, 358},
{ 0xC89C, 2, 3},
{ 0xC89E, 2, 65434},
{ 0xC8A0, 2, 65204},
{ 0xC8A2, 2, 589},
{ 0xC8A4, 2, 447},
{ 0xC8A6, 2, 65281},
{ 0xC8A8, 2, 65523},
{ 0xC8AA, 2, 65397},
{ 0xC8AC, 2, 408},
{ 0xC8AE, 2, 65533},
{ 0xC8B0, 2, 65434},
{ 0xC8B2, 2, 65255},
{ 0xC8B4, 2, 680},
{ 0xC8B6, 2, 473},
{ 0xC8B8, 2, 65318},
{ 0xC8BA, 2, 65523},
{ 0xC8BC, 2, 65459},
{ 0xC8BE, 2, 306},
{ 0xC8C0, 2, 65512},
{ 0xC8C2, 2, 65498},
{ 0xC8C4, 2, 65229},
{ 0xC8C6, 2, 706},
{ 0xC8C8, 2, 117},
{ 0xC8CA, 2, 284},
{ 0xC8CC, 2, 154},
{ 0xC8CE, 2, 261},
{ 0xC8D0, 2, 164},
{ 0xC8D2, 2, 172},
{ 0xC8D4, 2, 2700},
{ 0xC8D6, 2, 3850},
{ 0xC8D8, 2, 6500},
{ 0xC914, 2, 0},
{ 0xC916, 2, 0},
{ 0xC918, 2, 1279},
{ 0xC91A, 2, 719},
{ 0xC904, 2, 51},
{ 0xC906, 2, 64},
{ 0xC8F2, 1, 3},
{ 0xC8F3, 1, 2},
{ 0xC906, 2, 60},
{ 0xC8F4, 2, 0},
{ 0xC8F6, 2, 0},
{ 0xC8F8, 2, 0},
{ 0xC8FA, 2, 59172},
{ 0xC8FC, 2, 5507},
{ 0xC8FE, 2, 8261},
{ 0xC900, 2, 1023},
{ 0xC902, 2, 124},
{ 0xC90C, 1, 128},
{ 0xC90D, 1, 128},
{ 0xC90E, 1, 128},
{ 0xC90F, 1, 136},
{ 0xC910, 1, 128},
{ 0xC911, 1, 128},
{ 0xffff, 0xffff ,0xffff}
};
static struct regval_list uvc_ctrl_regs[] = {
{ REG_UVC_AE_MODE, 1, 0x02}, //has to be enabled by default, otherwise the camera will never start
{ REG_UVC_AUTO_WHITE_BALANCE_TEMPERATURE, 1, 0x01},
{ REG_UVC_AE_PRIORITY, 1, 0x00},
{ REG_UVC_POWER_LINE_FREQUENCY, 1, 0x02},
{ REG_UVC_EXPOSURE_TIME, 4, 0x00000001},
{ REG_UVC_BACKLIGHT_COMPENSATION, 2, 0x0001},
{ REG_UVC_BRIGHTNESS, 2, 0x0037},
{ REG_UVC_CONTRAST, 2, 0x0020},
{ REG_UVC_GAIN, 2, 0x0020},
{ REG_UVC_HUE, 2, 0x0000},
{ REG_UVC_SATURATION, 2, 0x0080},
{ REG_UVC_SHARPNESS, 2, -7},
{ REG_UVC_GAMMA, 2, 0x00DC},
{ REG_UVC_WHITE_BALANCE_TEMPERATURE, 2, 0x09C4},
{ REG_UVC_FRAME_INTERVAL, 4, 0x00000001},
{ REG_UVC_MANUAL_EXPOSURE, 1, 0x00}, //disable flicker avoidance, allow exposure time to be longer than the frame time.
{ REG_UVC_FLICKER_AVOIDANCE, 1, 0x00},
{ REG_UVC_ALGO, 2, 0x0007},
{ REG_UVC_RESULT_STATUS, 1, 0x00},
{ 0xffff, 0xffff ,0xffff}
};
static struct regval_list mt9m114_960p30_regs[] = {
{REG_LOGICAL_ADDRESS_ACCESS, 2, 0x0000},
{REG_CAM_SENSOR_CFG_Y_ADDR_START, 2, 4},
{REG_CAM_SENSOR_CFG_X_ADDR_START, 2, 4},
{REG_CAM_SENSOR_CFG_Y_ADDR_END, 2, 971},
{REG_CAM_SENSOR_CFG_X_ADDR_END, 2, 1291},
{REG_CAM_SENSOR_CFG_PIXCLK, 4, 48000000},
{REG_CAM_SENSOR_CFG_ROW_SPEED, 2, 0x0001},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN, 2, 219},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX, 2, 1480},
{REG_CAM_SENSOR_CFG_FRAME_LENGTH_LINES, 2, 1007},
{REG_CAM_SENSOR_CFG_LINE_LENGTH_PCK, 2, 1611},
{REG_CAM_SENSOR_CFG_FINE_CORRECTION, 2, 96},
{REG_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 963},
{REG_CAM_SENSOR_CFG_REG_0_DATA, 2, 0x0020},
// {REG_CAM_SENSOR_CONTROL_READ_MODE, 1, 0x0000},
{REG_CAM_CROP_WINDOW_XOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_YOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_WIDTH, 2, 1280},
{REG_CAM_CROP_WINDOW_HEIGHT, 2, 960},
{REG_CROP_CROPMODE, 1, 0x03},
{REG_CAM_OUTPUT_WIDTH, 2, 1280},
{REG_CAM_OUTPUT_HEIGHT, 2, 960},
{REG_CAM_AET_AEMODE, 1, 0x0},
{REG_CAM_AET_MAX_FRAME_RATE, 2, 0x1D97},
{REG_CAM_AET_MIN_FRAME_RATE, 2, 0x1D97},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 1279},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 959},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 255},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 191},
{ 0xffff, 0xffff ,0xffff } /* END MARKER */
};
static struct regval_list mt9m114_720p36_regs[] = {
{REG_LOGICAL_ADDRESS_ACCESS, 2, 0x0000},
{REG_CAM_SENSOR_CFG_Y_ADDR_START, 2, 124},
{REG_CAM_SENSOR_CFG_X_ADDR_START, 2, 4},
{REG_CAM_SENSOR_CFG_Y_ADDR_END, 2, 851},
{REG_CAM_SENSOR_CFG_X_ADDR_END, 2, 1291},
{REG_CAM_SENSOR_CFG_PIXCLK, 4, 48000000},
{REG_CAM_SENSOR_CFG_ROW_SPEED, 2, 0x0001},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN, 2, 219},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX, 2, 1558},
{REG_CAM_SENSOR_CFG_FRAME_LENGTH_LINES, 2, 778},
{REG_CAM_SENSOR_CFG_LINE_LENGTH_PCK, 2, 1689},
{REG_CAM_SENSOR_CFG_FINE_CORRECTION, 2, 96},
{REG_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 723},
{REG_CAM_SENSOR_CFG_REG_0_DATA, 2, 0x0020},
// {REG_CAM_SENSOR_CONTROL_READ_MODE, 1, 0x0000},
{REG_CAM_CROP_WINDOW_XOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_YOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_WIDTH, 2, 1280},
{REG_CAM_CROP_WINDOW_HEIGHT, 2, 720},
{REG_CROP_CROPMODE, 1, 0x03},
{REG_CAM_OUTPUT_WIDTH, 2, 1280},
{REG_CAM_OUTPUT_HEIGHT, 2, 720},
{REG_CAM_AET_AEMODE, 1, 0x00},
{REG_CAM_AET_MAX_FRAME_RATE, 2, 0x24AB},
{REG_CAM_AET_MIN_FRAME_RATE, 2, 0x24AB},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 1279},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 719},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 255},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 143},
{ 0xffff, 0xffff ,0xffff } /* END MARKER */
};
#if 0
static struct regval_list mt9m114_vga_30_to_75_binned_regs[] = {
{REG_LOGICAL_ADDRESS_ACCESS, 2, 0x0000},
{REG_CAM_SENSOR_CFG_Y_ADDR_START, 2, 0},
{REG_CAM_SENSOR_CFG_X_ADDR_START, 2, 0},
{REG_CAM_SENSOR_CFG_Y_ADDR_END, 2, 973},
{REG_CAM_SENSOR_CFG_X_ADDR_END, 2, 1293},
{REG_CAM_SENSOR_CFG_PIXCLK, 4, 48000000},
{REG_CAM_SENSOR_CFG_ROW_SPEED, 2, 1},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN, 2, 451},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX, 2, 948},
{REG_CAM_SENSOR_CFG_FRAME_LENGTH_LINES, 2, 541},
{REG_CAM_SENSOR_CFG_LINE_LENGTH_PCK, 2, 1183},
{REG_CAM_SENSOR_CFG_FINE_CORRECTION, 2, 224},
{REG_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 484},
{REG_CAM_SENSOR_CFG_REG_0_DATA, 2, 0x0020},
//{REG_CAM_SENSOR_CONTROL_READ_MODE, 1, 0x0000},
{REG_CAM_CROP_WINDOW_XOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_YOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_WIDTH, 2, 640},
{REG_CAM_CROP_WINDOW_HEIGHT, 2, 481},
{REG_CROP_CROPMODE, 1, 3},
{REG_CAM_OUTPUT_WIDTH, 2, 640},
{REG_CAM_OUTPUT_HEIGHT, 2, 481},
{REG_CAM_AET_AEMODE, 1, 0x00},
{REG_CAM_AET_MAX_FRAME_RATE, 2, 0x4B00},
{REG_CAM_AET_MIN_FRAME_RATE, 2, 0x1E00},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 639},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 480},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 127},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 95},
// {REG_AUTO_BINNING_MODE,1, 0x00},
{ 0xffff, 0xffff ,0xffff }
};
#endif
static struct regval_list mt9m114_vga_30_scaling_regs[] = {
{REG_LOGICAL_ADDRESS_ACCESS, 2, 0x0000},
{REG_CAM_SENSOR_CFG_Y_ADDR_START, 2, 4},
{REG_CAM_SENSOR_CFG_X_ADDR_START, 2, 4},
{REG_CAM_SENSOR_CFG_Y_ADDR_END, 2, 971},
{REG_CAM_SENSOR_CFG_X_ADDR_END, 2, 1291},
{REG_CAM_SENSOR_CFG_PIXCLK, 4, 48000000},
{REG_CAM_SENSOR_CFG_ROW_SPEED, 2, 1},//FIXME according to the documentation this value is unused, however we still set the default. No idea why
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN, 2, 219},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX, 2, 1460},
{REG_CAM_SENSOR_CFG_FRAME_LENGTH_LINES, 2, 1006},//FIXME might be a typo. default value is 1007
{REG_CAM_SENSOR_CFG_LINE_LENGTH_PCK, 2, 1591},//FIXME might be a typo? default is 1589
{REG_CAM_SENSOR_CFG_FINE_CORRECTION, 2, 96},
{REG_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 963},
{REG_CAM_SENSOR_CFG_REG_0_DATA, 2, 0x0020},
// {REG_CAM_SENSOR_CONTROL_READ_MODE, 1, 0x0000},
{REG_CAM_CROP_WINDOW_XOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_YOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_WIDTH, 2, 1280},
{REG_CAM_CROP_WINDOW_HEIGHT, 2, 960},
{REG_CROP_CROPMODE, 1, 3},
{REG_CAM_OUTPUT_WIDTH, 2, 640},
{REG_CAM_OUTPUT_HEIGHT, 2, 480},
{REG_CAM_AET_AEMODE, 1, 0x00},
{REG_CAM_AET_MAX_FRAME_RATE, 2, 0x1DFD},
{REG_CAM_AET_MIN_FRAME_RATE, 2, 0x1DFD},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 639},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 479},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 127},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 95},
// {REG_AUTO_BINNING_MODE,1, 0x00},
{ 0xffff, 0xffff ,0xffff }//array end,
};
#if 0
static struct regval_list mt9m114_qvga_30_to_120_binned_regs[] = {
{REG_LOGICAL_ADDRESS_ACCESS, 2, 0x0000},
{REG_CAM_SENSOR_CFG_Y_ADDR_START, 2, 238},
{REG_CAM_SENSOR_CFG_X_ADDR_START, 2, 320},
{REG_CAM_SENSOR_CFG_Y_ADDR_END, 2, 733},
{REG_CAM_SENSOR_CFG_X_ADDR_END, 2, 973},
{REG_CAM_SENSOR_CFG_PIXCLK, 4, 48000000},
{REG_CAM_SENSOR_CFG_ROW_SPEED, 2, 1},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN, 2, 451},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX, 2, 648},
{REG_CAM_SENSOR_CFG_FRAME_LENGTH_LINES, 2, 453},
{REG_CAM_SENSOR_CFG_LINE_LENGTH_PCK, 2, 883},
{REG_CAM_SENSOR_CFG_FINE_CORRECTION, 2, 224},
{REG_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 244},
{REG_CAM_SENSOR_CFG_REG_0_DATA, 2, 0x0020},
// {REG_CAM_SENSOR_CONTROL_READ_MODE, 1, 0x0000},
{REG_CAM_CROP_WINDOW_XOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_YOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_WIDTH, 2, 320},
{REG_CAM_CROP_WINDOW_HEIGHT, 2, 241},
{REG_CROP_CROPMODE, 1, 3},
{REG_CAM_OUTPUT_WIDTH, 2, 320},
{REG_CAM_OUTPUT_HEIGHT, 2, 241},
{REG_CAM_AET_AEMODE, 1, 0x00},
{REG_CAM_AET_MAX_FRAME_RATE, 2, 0x7800},
{REG_CAM_AET_MIN_FRAME_RATE, 2, 0x1E00},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 319},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 240},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 63},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 47},
// {REG_AUTO_BINNING_MODE,1, 0x00},
{ 0xffff, 0xffff ,0xffff }
};
#endif
static struct regval_list mt9m114_qvga_30_scaling_regs[] = {
{REG_LOGICAL_ADDRESS_ACCESS, 2, 0x0000},
{REG_CAM_SENSOR_CFG_Y_ADDR_START, 2, 4},
{REG_CAM_SENSOR_CFG_X_ADDR_START, 2, 4},
{REG_CAM_SENSOR_CFG_Y_ADDR_END, 2, 971},
{REG_CAM_SENSOR_CFG_X_ADDR_END, 2, 1291},
{REG_CAM_SENSOR_CFG_PIXCLK, 4, 48000000},
{REG_CAM_SENSOR_CFG_ROW_SPEED, 2, 1},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN, 2, 219},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX, 2, 1460},
{REG_CAM_SENSOR_CFG_FRAME_LENGTH_LINES, 2, 1006},
{REG_CAM_SENSOR_CFG_LINE_LENGTH_PCK, 2, 1591},
{REG_CAM_SENSOR_CFG_FINE_CORRECTION, 2, 96},
{REG_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 963},
{REG_CAM_SENSOR_CFG_REG_0_DATA, 2, 0x0020},
//{REG_CAM_SENSOR_CONTROL_READ_MODE, 1, 0x0000},
{REG_CAM_CROP_WINDOW_XOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_YOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_WIDTH, 2, 1280},
{REG_CAM_CROP_WINDOW_HEIGHT, 2, 960},
{REG_CROP_CROPMODE, 1, 3},
{REG_CAM_OUTPUT_WIDTH, 2, 320},
{REG_CAM_OUTPUT_HEIGHT, 2, 240},
{REG_CAM_AET_AEMODE, 1, 0x00},
{REG_CAM_AET_MAX_FRAME_RATE, 2, 0x1DFD},
{REG_CAM_AET_MIN_FRAME_RATE, 2, 0x1DFD},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 319},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 239},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 63},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 47},
// {REG_AUTO_BINNING_MODE,1, 0x00},
{ 0xffff, 0xffff ,0xffff }
};
#if 0
static struct regval_list mt9m114_160x120_30_to_120_binned_regs[] = {
{REG_LOGICAL_ADDRESS_ACCESS, 2, 0x0000},
{REG_CAM_SENSOR_CFG_Y_ADDR_START, 2, 358},
{REG_CAM_SENSOR_CFG_X_ADDR_START, 2, 480},
{REG_CAM_SENSOR_CFG_Y_ADDR_END, 2, 613},
{REG_CAM_SENSOR_CFG_X_ADDR_END, 2, 813},
{REG_CAM_SENSOR_CFG_PIXCLK, 4, 48000000},
{REG_CAM_SENSOR_CFG_ROW_SPEED, 2, 1},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN, 2, 451},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX, 2, 648},
{REG_CAM_SENSOR_CFG_FRAME_LENGTH_LINES, 2, 453},
{REG_CAM_SENSOR_CFG_LINE_LENGTH_PCK, 2, 883},
{REG_CAM_SENSOR_CFG_FINE_CORRECTION, 2, 224},
{REG_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 124},
{REG_CAM_SENSOR_CFG_REG_0_DATA, 2, 0x0020},
//{REG_CAM_SENSOR_CONTROL_READ_MODE, 1, 0x0000},
{REG_CAM_CROP_WINDOW_XOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_YOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_WIDTH, 2, 160},
{REG_CAM_CROP_WINDOW_HEIGHT, 2, 121},
{REG_CROP_CROPMODE, 1, 3},
{REG_CAM_OUTPUT_WIDTH, 2, 160},
{REG_CAM_OUTPUT_HEIGHT, 2, 121},
{REG_CAM_AET_AEMODE, 1, 0x00},
{REG_CAM_AET_MAX_FRAME_RATE, 2, 0x7800},
{REG_CAM_AET_MIN_FRAME_RATE, 2, 0x1E00},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 159},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 120},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 31},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 23},
// {REG_AUTO_BINNING_MODE,1, 0x00},
{ 0xffff, 0xffff ,0xffff }
};
#endif
static struct regval_list mt9m114_160x120_30_scaling_regs[] = {
{REG_LOGICAL_ADDRESS_ACCESS, 2, 0x0000},
{REG_CAM_SENSOR_CFG_Y_ADDR_START, 2, 4},
{REG_CAM_SENSOR_CFG_X_ADDR_START, 2, 4},
{REG_CAM_SENSOR_CFG_Y_ADDR_END, 2, 971},
{REG_CAM_SENSOR_CFG_X_ADDR_END, 2, 1291},
{REG_CAM_SENSOR_CFG_PIXCLK, 4, 48000000},
{REG_CAM_SENSOR_CFG_ROW_SPEED, 2, 1},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN, 2, 219},
{REG_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX, 2, 1460},
{REG_CAM_SENSOR_CFG_FRAME_LENGTH_LINES, 2, 1006},
{REG_CAM_SENSOR_CFG_LINE_LENGTH_PCK, 2, 1591},
{REG_CAM_SENSOR_CFG_FINE_CORRECTION, 2, 96},
{REG_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 963},
{REG_CAM_SENSOR_CFG_REG_0_DATA, 2, 0x0020},
//{REG_CAM_SENSOR_CONTROL_READ_MODE, 1, 0x0000},
{REG_CAM_CROP_WINDOW_XOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_YOFFSET, 2, 0x0000},
{REG_CAM_CROP_WINDOW_WIDTH, 2, 1280},
{REG_CAM_CROP_WINDOW_HEIGHT, 2, 960},
{REG_CROP_CROPMODE, 1, 3},
{REG_CAM_OUTPUT_WIDTH, 2, 160},
{REG_CAM_OUTPUT_HEIGHT, 2, 120},
{REG_CAM_AET_AEMODE, 1, 0x00},
{REG_CAM_AET_MAX_FRAME_RATE, 2, 0x1DFD},
{REG_CAM_AET_MIN_FRAME_RATE, 2, 0x1DFD},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 159},
{REG_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 119},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YSTART, 2, 0x0000},
{REG_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 31},
{REG_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 23},
// {REG_AUTO_BINNING_MODE,1, 0x00},
{ 0xffff, 0xffff ,0xffff }
};
/*
* Here we'll try to encapsulate the changes for just the output
* video format.
*
*/
static struct regval_list mt9m114_fmt_yuv422[] = {
{REG_CAM_OUTPUT_FORMAT, 2, 0x000A},
{REG_CAM_OUTPUT_OFFSET, 1, 0x10},
{REG_CAM_OUPUT_FORMAT_YUV, 2, 0x1A},
{ 0xffff, 0xffff, 0xffff },
};
//forward declarations
static int mt9m114_wait_num_frames(struct v4l2_subdev *sd, u16 numFrames);
static int mt9m114_g_exposure(struct v4l2_subdev *sd, s32 *value);
static int mt9m114_s_exposure(struct v4l2_subdev *sd, u32 value);
static int mt9m114_g_gain(struct v4l2_subdev *sd, s32 *value);
static int mt9m114_s_gain(struct v4l2_subdev *sd, int value);
static int mt9m114_g_brightness(struct v4l2_subdev *sd, s32 *value);
static int mt9m114_s_brightness(struct v4l2_subdev *sd, int value);
static int mt9m114_g_contrast(struct v4l2_subdev *sd, s32 *value);
static int mt9m114_s_contrast(struct v4l2_subdev *sd, int value);
static int mt9m114_g_sat(struct v4l2_subdev *sd, s32 *value);
static int mt9m114_s_sat(struct v4l2_subdev *sd, int value);
static int mt9m114_g_sharpness(struct v4l2_subdev *sd, s32 *value);
static int mt9m114_s_sharpness(struct v4l2_subdev *sd, int value);
static int mt9m114_g_hue(struct v4l2_subdev *sd, s32 *value);
/*
* Low-level register I/O.
*/
static int mt9m114_read(struct v4l2_subdev *sd,
u16 reg,
u16 size,
u32 *value)
{
u8 cmd[10];
struct i2c_client *client = v4l2_get_subdevdata(sd);
cmd[0] = reg/256;
cmd[1] = reg%256;
i2c_master_send(client, cmd, 2); //FIXME these functions return error codes. Check them.
i2c_master_recv(client, cmd, size);
if( size == 2 )
{
*value = (((u32)cmd[0])<<8) + cmd[1];
}
else if( size == 4 )
{
*value = (((u32)cmd[0])<<24) + (((u32)cmd[1])<<16) +
(((u32)cmd[2])<<8) + (((u32)cmd[3])<<0);
}
else if( size == 1 )
{
*value = cmd[0];
}
return 0;
}
#define MAX_MASTER_WRITE 48
static int mt9m114_burst_write(struct v4l2_subdev *sd,
u16 reg,
u16 * array,
u16 size)
{
int i=0;
int index=0, abs_index=0;
int packet_size=0;
u8 cmd[255];
struct i2c_client *client = v4l2_get_subdevdata(sd);
while(size)
{
if (size >= MAX_MASTER_WRITE){
packet_size = MAX_MASTER_WRITE;
}
else{
packet_size = size;
}
size -= packet_size;
index = 0;
cmd[index++] = reg/256;
cmd[index++] = reg%256;
for (i = 0;i < packet_size; i++)
{
u16 val = array[abs_index++];
cmd[index++] = val / 256;
cmd[index++] = val % 256;
reg +=2;
}
i2c_master_send(client, cmd, index);
}
return 0;
}
/**
*
* @param sd
* @param reg
* @param size
* @param value
* @return 0 in case of success. Errno error code otherwise.
*/
static int mt9m114_write(struct v4l2_subdev *sd,
u16 reg,
u16 size,
u32 value)
{
u8 cmd[10];
int index=0;
struct i2c_client *client = v4l2_get_subdevdata(sd);
int numBytesWritten = 0;
cmd[index++] = reg/256;
cmd[index++] = reg%256;
if( size == 2)
{
//FIXME this breaks signedness.
cmd[index++] = value/256;
cmd[index++] = value%256;
}
else if( size == 4)
{
cmd[index++] = value>>24 & 0xff;
cmd[index++] = value>>16 & 0xff;
cmd[index++] = value>>8 & 0xff;
cmd[index++] = value>>0 & 0xff;
}
else if( size == 1)
{
cmd[index++] = value;
}