Parsing Problem - Output Port and Record Member with the same name

[orsc]

In veditor 1.2:
The following code produces this error:
/vhdl_test line 22 "Output outp cannot be used in an expression"
Thats the assigment to "parsing_problem". As it can be seen this type of asigment only fails if inside an process.

library ieee;
use ieee.std_logic_1164.all;

entity tst is
    port  (
        outp : out std_logic
    );
end tst;

architecture arch of tst is
    type r is record
        outp : std_logic;
    end record;
    signal ok_1,ok_2,parsing_problem : r;
begin

    ok_1 <= ( outp => '1');

    p : process
    begin
        ok_2.outp    <= '1';
        parsing_problem <= (outp => '1');
    end process;
end arch;

[ssharks]

Thanks for reporting, I had too look at the problem at least three times before I understood the problem.
The problem is not really in the parser itself, but more in the checks that are added afterwards. The outline etc. should still work.
I will take a look at it, but it might take a while. Feel free to take a look at the issue yourself.

[ssharks]

Dear orsc,

It has been a while, but I think I fixed your problem in the new release. Can you give it a try?

package_1.2.1.16.zip