Skip to content

Commit 5698042

Browse files
CMGeldenhuysfpistm
authored andcommitted
variants(f4): add Nucleo-F446ZE
1 parent 9767755 commit 5698042

File tree

4 files changed

+536
-0
lines changed

4 files changed

+536
-0
lines changed

README.md

+1
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
9191
| :green_heart: | STM32F412ZG | [Nucleo F412ZG](http://www.st.com/en/evaluation-tools/nucleo-f412zg.html) | *2.6.0* | |
9292
| :green_heart: | STM32F413ZH | [Nucleo F413ZH](http://www.st.com/en/evaluation-tools/nucleo-f413zh.html) | *2.4.0* | |
9393
| :green_heart: | STM32F429ZI | [Nucleo F429ZI](http://www.st.com/en/evaluation-tools/nucleo-f429zi.html) | *0.1.0* | |
94+
| :yellow_heart: | STM32F446ZE | [Nucleo F446ZE](http://www.st.com/en/evaluation-tools/nucleo-f446ze.html) | **2.7.0** | |
9495
| :green_heart: | STM32F722ZE | [Nucleo F722ZE](http://www.st.com/en/evaluation-tools/nucleo-f722ze.html) | *2.4.0* | |
9596
| :green_heart: | STM32F767ZI | [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) | *1.4.0* | |
9697
| :green_heart: | STM32F746ZG | [Nucleo F746ZG](https://www.st.com/en/evaluation-tools/nucleo-f746zg.html) | *1.9.0* | |

boards.txt

+13
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,19 @@ Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.series=STM32F4xx
7676
Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.product_line=STM32F429xx
7777
Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.variant=STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)
7878

79+
# NUCLEO_F446RE board
80+
Nucleo_144.menu.pnum.NUCLEO_F446ZE=Nucleo F446ZE
81+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.node=NODE_F446ZE
82+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.upload.maximum_size=524288
83+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.upload.maximum_data_size=131072
84+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.mcu=cortex-m4
85+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.fpu=-mfpu=fpv4-sp-d16
86+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.float-abi=-mfloat-abi=hard
87+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.board=NUCLEO_F446ZE
88+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.series=STM32F4xx
89+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.product_line=STM32F446xx
90+
Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.variant=STM32F4xx/F446Z(C-E)(H-J-T)
91+
7992
# NUCLEO_F722ZE board
8093
Nucleo_144.menu.pnum.NUCLEO_F722ZE=Nucleo F722ZE
8194
Nucleo_144.menu.pnum.NUCLEO_F722ZE.node=NODE_F722ZE
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,245 @@
1+
/*
2+
*******************************************************************************
3+
* Copyright (c) 2023, STMicroelectronics
4+
* All rights reserved.
5+
*
6+
* This software component is licensed by ST under BSD 3-Clause license,
7+
* the "License"; You may not use this file except in compliance with the
8+
* License. You may obtain a copy of the License at:
9+
* opensource.org/licenses/BSD-3-Clause
10+
*
11+
*******************************************************************************
12+
*/
13+
#if defined(ARDUINO_NUCLEO_F446ZE)
14+
15+
#include "pins_arduino.h"
16+
17+
// Pin number
18+
const PinName digitalPin[] = {
19+
PG_9, //D0
20+
PG_14, //D1
21+
PF_15, //D2
22+
PE_13, //D3
23+
PF_14, //D4
24+
PE_11, //D5
25+
PE_9, //D6
26+
PF_13, //D7
27+
PF_12, //D8
28+
PD_15, //D9
29+
PD_14, //D10
30+
PA_7, //D11
31+
PA_6, //D12
32+
PA_5, //D13
33+
PB_9, //D14
34+
PB_8, //D15
35+
PC_6, //D16
36+
PB_15, //D17
37+
PB_13, //D18
38+
PB_12, //D19
39+
PA_15, //D20
40+
PC_7, //D21
41+
PB_5, //D22
42+
PB_3, //D23
43+
PA_4, //D24
44+
PB_4, //D25
45+
PB_6, //D26
46+
PB_2, //D27
47+
PD_13, //D28
48+
PD_12, //D29
49+
PD_11, //D30
50+
PE_2, //D31
51+
PA_0, //D32
52+
PB_0, //D33/A23 - LED_GREEN
53+
PE_0, //D34
54+
PB_11, //D35
55+
PB_10, //D36
56+
PE_15, //D37
57+
PE_14, //D38
58+
PE_12, //D39
59+
PE_10, //D40
60+
PE_7, //D41
61+
PE_8, //D42
62+
PC_8, //D43
63+
PC_9, //D44
64+
PC_10, //D45
65+
PC_11, //D46
66+
PC_12, //D47
67+
PD_2, //D48
68+
PG_2, //D49
69+
PG_3, //D50
70+
PD_7, //D51
71+
PD_6, //D52
72+
PD_5, //D53
73+
PD_4, //D54
74+
PD_3, //D55
75+
PE_2, //D56
76+
PE_4, //D57
77+
PE_5, //D58
78+
PE_6, //D59
79+
PE_3, //D60
80+
PF_8, //D61
81+
PF_7, //D62
82+
PF_9, //D63
83+
PG_1, //D64
84+
PG_0, //D65
85+
PD_1, //D66
86+
PD_0, //D67
87+
PF_0, //D68
88+
PF_1, //D69
89+
PF_2, //D70
90+
NC, //D71
91+
NC, //D72
92+
PB_7, //D73 - LED_BLUE
93+
PB_14, //D74 - LED_RED
94+
PC_13, //D75 - USER_BTN
95+
PD_9, //D76 - Serial Rx
96+
PD_8, //D77 - Serial Tx
97+
PA_3, //D78/A0
98+
PC_0, //D79/A1
99+
PC_3, //D80/A2
100+
PF_3, //D81/A3
101+
PF_5, //D82/A4
102+
PF_10, //D83/A5
103+
PB_1, //D84/A6
104+
PC_2, //D85/A7
105+
PF_4, //D86/A8
106+
PF_6, //D87/A9
107+
PA_1, //D88/A18
108+
PA_2, //D89/A19
109+
PA_8, //D90
110+
PA_9, //D91
111+
PA_10, //D92
112+
PA_11, //D93
113+
PA_12, //D94
114+
PA_13, //D95
115+
PA_14, //D96
116+
PC_1, //D97/A20
117+
PC_4, //D98/A21
118+
PC_5, //D99/A22
119+
PC_14, //D100
120+
PC_15, //D101
121+
PD_10, //D102
122+
PE_1, //D103
123+
PF_11, //D104
124+
PG_4, //D105
125+
PG_5, //D106
126+
PG_6, //D107
127+
PG_7, //D108
128+
PG_8, //D109
129+
PG_10, //D110
130+
PG_11, //D111
131+
PG_12, //D112
132+
PG_13, //D113
133+
PG_15, //D114
134+
PH_0, //D115
135+
PH_1 //D116
136+
};
137+
138+
// Analog (Ax) pin number array
139+
const uint32_t analogInputPin[] = {
140+
78, //A0
141+
79, //A1
142+
80, //A2
143+
81, //A3
144+
82, //A4
145+
83, //A5
146+
84, //A6
147+
85, //A7
148+
86, //A8
149+
87, //A9
150+
11, //A10
151+
12, //A11
152+
13, //A12
153+
24, //A13
154+
32, //A14
155+
61, //A15
156+
62, //A16
157+
63, //A17
158+
88, //A18
159+
89, //A19
160+
97, //A20
161+
98, //A21
162+
99, //A22
163+
33 //A23
164+
};
165+
166+
// ----------------------------------------------------------------------------
167+
168+
#ifdef __cplusplus
169+
extern "C" {
170+
#endif
171+
172+
/**
173+
* @brief System Clock Configuration
174+
* @param None
175+
* @retval None
176+
*/
177+
WEAK void SystemClock_Config(void)
178+
{
179+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
180+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
181+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
182+
183+
/** Configure LSE Drive Capability
184+
*/
185+
HAL_PWR_EnableBkUpAccess();
186+
187+
/** Configure the main internal regulator output voltage
188+
*/
189+
__HAL_RCC_PWR_CLK_ENABLE();
190+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
191+
192+
/** Initializes the RCC Oscillators according to the specified parameters
193+
* in the RCC_OscInitTypeDef structure.
194+
*/
195+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
196+
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
197+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
198+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
199+
RCC_OscInitStruct.PLL.PLLM = 4;
200+
RCC_OscInitStruct.PLL.PLLN = 180;
201+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
202+
RCC_OscInitStruct.PLL.PLLQ = 7;
203+
RCC_OscInitStruct.PLL.PLLR = 2;
204+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
205+
Error_Handler();
206+
}
207+
208+
/** Activate the Over-Drive mode
209+
*/
210+
if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
211+
Error_Handler();
212+
}
213+
214+
/** Initializes the CPU, AHB and APB buses clocks
215+
*/
216+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
217+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
218+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
219+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
220+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
221+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
222+
223+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
224+
Error_Handler();
225+
}
226+
227+
/** Initializes the peripherals clock
228+
*/
229+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_CLK48;
230+
PeriphClkInitStruct.PLLSAI.PLLSAIM = 4;
231+
PeriphClkInitStruct.PLLSAI.PLLSAIN = 96;
232+
PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
233+
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
234+
PeriphClkInitStruct.PLLSAIDivQ = 1;
235+
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
236+
PeriphClkInitStruct.SdioClockSelection = RCC_SDIOCLKSOURCE_CLK48;
237+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
238+
Error_Handler();
239+
}
240+
}
241+
242+
#ifdef __cplusplus
243+
}
244+
#endif
245+
#endif /* ARDUINO_NUCLEO_L476RG */

0 commit comments

Comments
 (0)