Skip to content

Commit 5809912

Browse files
fpistmfpistm
authored
Merge pull request #1058 from fpistm/CubeUpdateL4
Update to latest STM32CubeL4
2 parents 394704d + 46940ef commit 5809912

26 files changed

+632
-425
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4p5xx.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15773,6 +15773,9 @@ typedef struct
1577315773
#define OCTOSPI_DCR1_FRCK_Pos (1U)
1577415774
#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
1577515775
#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
15776+
#define OCTOSPI_DCR1_DLYBYP_Pos (1U)
15777+
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */
15778+
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */
1577615779
#define OCTOSPI_DCR1_CSHT_Pos (8U)
1577715780
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
1577815781
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -15798,6 +15801,9 @@ typedef struct
1579815801
#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
1579915802

1580015803
/**************** Bit definition for OCTOSPI_DCR3 register ******************/
15804+
#define OCTOSPI_DCR3_MAXTRAN_Pos (0U)
15805+
#define OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */
15806+
#define OCTOSPI_DCR3_MAXTRAN OCTOSPI_DCR3_MAXTRAN_Msk /*!< Maximum Transfer */
1580115807
#define OCTOSPI_DCR3_CSBOUND_Pos (16U)
1580215808
#define OCTOSPI_DCR3_CSBOUND_Msk (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */
1580315809
#define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk /*!< CS Boundary */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4q5xx.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16284,6 +16284,9 @@ typedef struct
1628416284
#define OCTOSPI_DCR1_FRCK_Pos (1U)
1628516285
#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
1628616286
#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
16287+
#define OCTOSPI_DCR1_DLYBYP_Pos (1U)
16288+
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */
16289+
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */
1628716290
#define OCTOSPI_DCR1_CSHT_Pos (8U)
1628816291
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
1628916292
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -16309,6 +16312,9 @@ typedef struct
1630916312
#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
1631016313

1631116314
/**************** Bit definition for OCTOSPI_DCR3 register ******************/
16315+
#define OCTOSPI_DCR3_MAXTRAN_Pos (0U)
16316+
#define OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */
16317+
#define OCTOSPI_DCR3_MAXTRAN OCTOSPI_DCR3_MAXTRAN_Msk /*!< Maximum Transfer */
1631216318
#define OCTOSPI_DCR3_CSBOUND_Pos (16U)
1631316319
#define OCTOSPI_DCR3_CSBOUND_Msk (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */
1631416320
#define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk /*!< CS Boundary */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14791,6 +14791,9 @@ typedef struct
1479114791
#define OCTOSPI_DCR1_FRCK_Pos (1U)
1479214792
#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
1479314793
#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
14794+
#define OCTOSPI_DCR1_DLYBYP_Pos (1U)
14795+
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */
14796+
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */
1479414797
#define OCTOSPI_DCR1_CSHT_Pos (8U)
1479514798
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
1479614799
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r7xx.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15290,6 +15290,9 @@ typedef struct
1529015290
#define OCTOSPI_DCR1_FRCK_Pos (1U)
1529115291
#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
1529215292
#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
15293+
#define OCTOSPI_DCR1_DLYBYP_Pos (1U)
15294+
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */
15295+
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */
1529315296
#define OCTOSPI_DCR1_CSHT_Pos (8U)
1529415297
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
1529515298
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18422,6 +18422,9 @@ typedef struct
1842218422
#define OCTOSPI_DCR1_FRCK_Pos (1U)
1842318423
#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
1842418424
#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
18425+
#define OCTOSPI_DCR1_DLYBYP_Pos (1U)
18426+
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */
18427+
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */
1842518428
#define OCTOSPI_DCR1_CSHT_Pos (8U)
1842618429
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
1842718430
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s5xx.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15138,6 +15138,9 @@ typedef struct
1513815138
#define OCTOSPI_DCR1_FRCK_Pos (1U)
1513915139
#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
1514015140
#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
15141+
#define OCTOSPI_DCR1_DLYBYP_Pos (1U)
15142+
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */
15143+
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */
1514115144
#define OCTOSPI_DCR1_CSHT_Pos (8U)
1514215145
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
1514315146
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s7xx.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15637,6 +15637,9 @@ typedef struct
1563715637
#define OCTOSPI_DCR1_FRCK_Pos (1U)
1563815638
#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
1563915639
#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
15640+
#define OCTOSPI_DCR1_DLYBYP_Pos (1U)
15641+
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */
15642+
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */
1564015643
#define OCTOSPI_DCR1_CSHT_Pos (8U)
1564115644
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
1564215645
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s9xx.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18769,6 +18769,9 @@ typedef struct
1876918769
#define OCTOSPI_DCR1_FRCK_Pos (1U)
1877018770
#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
1877118771
#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
18772+
#define OCTOSPI_DCR1_DLYBYP_Pos (1U)
18773+
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */
18774+
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */
1877218775
#define OCTOSPI_DCR1_CSHT_Pos (8U)
1877318776
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
1877418777
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,7 @@
107107
*/
108108
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
109109
#define __STM32L4_CMSIS_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
110-
#define __STM32L4_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
110+
#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
111111
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
112112
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
113113
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\

0 commit comments

Comments
 (0)