Skip to content

Commit 754305f

Browse files
fpistmfpistm
committed
Updated STM32F3xx CMSIS to v2.3.2
Included in STM32CubeF3 FW V1.9.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent f25024c commit 754305f

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

47 files changed

+325
-2702
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h‎

Lines changed: 32 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32f301x8.h
44
* @author MCD Application Team
5-
* @version V2.3.1
6-
* @date 16-December-2016
75
* @brief CMSIS STM32F301x8 Devices Peripheral Access Layer Header File.
86
*
97
* This file contains:
@@ -3541,9 +3539,19 @@ typedef struct
35413539
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
35423540
#endif
35433541

3542+
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
35443543
#define EXTI_IMR2_IM_Pos (0U)
35453544
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
35463545
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
3546+
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
3547+
#define EXTI_IMR2_IM_Pos (0U)
3548+
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
3549+
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
3550+
#else
3551+
#define EXTI_IMR2_IM_Pos (0U)
3552+
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
3553+
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
3554+
#endif
35473555

35483556
/******************* Bit definition for EXTI_EMR2 ****************************/
35493557
#define EXTI_EMR2_MR32_Pos (0U)
@@ -3562,6 +3570,20 @@ typedef struct
35623570
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
35633571
#endif
35643572

3573+
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
3574+
#define EXTI_EMR2_EM_Pos (0U)
3575+
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
3576+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
3577+
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
3578+
#define EXTI_EMR2_EM_Pos (0U)
3579+
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
3580+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
3581+
#else
3582+
#define EXTI_EMR2_EM_Pos (0U)
3583+
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
3584+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
3585+
#endif
3586+
35653587
/****************** Bit definition for EXTI_RTSR2 register ********************/
35663588
#define EXTI_RTSR2_TR32_Pos (0U)
35673589
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@@ -3811,21 +3833,6 @@ typedef struct
38113833
#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
38123834
#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
38133835

3814-
/****************** Bit definition for FLASH_WRP2 register ******************/
3815-
#define OB_WRP2_WRP2_Pos (0U)
3816-
#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
3817-
#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
3818-
#define OB_WRP2_nWRP2_Pos (8U)
3819-
#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
3820-
#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
3821-
3822-
/****************** Bit definition for FLASH_WRP3 register ******************/
3823-
#define OB_WRP3_WRP3_Pos (16U)
3824-
#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
3825-
#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
3826-
#define OB_WRP3_nWRP3_Pos (24U)
3827-
#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
3828-
#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
38293836

38303837
/******************************************************************************/
38313838
/* */
@@ -5442,9 +5449,9 @@ typedef struct
54425449
#define RTC_CR_COSEL_Pos (19U)
54435450
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
54445451
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
5445-
#define RTC_CR_BCK_Pos (18U)
5446-
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
5447-
#define RTC_CR_BCK RTC_CR_BCK_Msk
5452+
#define RTC_CR_BKP_Pos (18U)
5453+
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
5454+
#define RTC_CR_BKP RTC_CR_BKP_Msk
54485455
#define RTC_CR_SUB1H_Pos (17U)
54495456
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
54505457
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@@ -5494,6 +5501,11 @@ typedef struct
54945501
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
54955502
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
54965503

5504+
/* Legacy defines */
5505+
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
5506+
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
5507+
#define RTC_CR_BCK RTC_CR_BKP
5508+
54975509
/******************** Bits definition for RTC_ISR register ******************/
54985510
#define RTC_ISR_RECALPF_Pos (16U)
54995511
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

‎system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h‎

Lines changed: 32 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32f302x8.h
44
* @author MCD Application Team
5-
* @version V2.3.1
6-
* @date 16-December-2016
75
* @brief CMSIS STM32F302x8 Devices Peripheral Access Layer Header File.
86
*
97
* This file contains:
@@ -7137,9 +7135,19 @@ typedef struct
71377135
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
71387136
#endif
71397137

7138+
#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
71407139
#define EXTI_IMR2_IM_Pos (0U)
71417140
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
71427141
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
7142+
#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
7143+
#define EXTI_IMR2_IM_Pos (0U)
7144+
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
7145+
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
7146+
#else
7147+
#define EXTI_IMR2_IM_Pos (0U)
7148+
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
7149+
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
7150+
#endif
71437151

71447152
/******************* Bit definition for EXTI_EMR2 ****************************/
71457153
#define EXTI_EMR2_MR32_Pos (0U)
@@ -7158,6 +7166,20 @@ typedef struct
71587166
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
71597167
#endif
71607168

7169+
#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
7170+
#define EXTI_EMR2_EM_Pos (0U)
7171+
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
7172+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
7173+
#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
7174+
#define EXTI_EMR2_EM_Pos (0U)
7175+
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
7176+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
7177+
#else
7178+
#define EXTI_EMR2_EM_Pos (0U)
7179+
#define EXTI_EMR2_EM_Msk (0x1U << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */
7180+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
7181+
#endif
7182+
71617183
/****************** Bit definition for EXTI_RTSR2 register ********************/
71627184
#define EXTI_RTSR2_TR32_Pos (0U)
71637185
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@@ -7407,21 +7429,6 @@ typedef struct
74077429
#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
74087430
#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
74097431

7410-
/****************** Bit definition for FLASH_WRP2 register ******************/
7411-
#define OB_WRP2_WRP2_Pos (0U)
7412-
#define OB_WRP2_WRP2_Msk (0xFFU << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */
7413-
#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
7414-
#define OB_WRP2_nWRP2_Pos (8U)
7415-
#define OB_WRP2_nWRP2_Msk (0xFFU << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
7416-
#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
7417-
7418-
/****************** Bit definition for FLASH_WRP3 register ******************/
7419-
#define OB_WRP3_WRP3_Pos (16U)
7420-
#define OB_WRP3_WRP3_Msk (0xFFU << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
7421-
#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
7422-
#define OB_WRP3_nWRP3_Pos (24U)
7423-
#define OB_WRP3_nWRP3_Msk (0xFFU << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
7424-
#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
74257432

74267433
/******************************************************************************/
74277434
/* */
@@ -9058,9 +9065,9 @@ typedef struct
90589065
#define RTC_CR_COSEL_Pos (19U)
90599066
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
90609067
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
9061-
#define RTC_CR_BCK_Pos (18U)
9062-
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
9063-
#define RTC_CR_BCK RTC_CR_BCK_Msk
9068+
#define RTC_CR_BKP_Pos (18U)
9069+
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
9070+
#define RTC_CR_BKP RTC_CR_BKP_Msk
90649071
#define RTC_CR_SUB1H_Pos (17U)
90659072
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
90669073
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@@ -9110,6 +9117,11 @@ typedef struct
91109117
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
91119118
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
91129119

9120+
/* Legacy defines */
9121+
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
9122+
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
9123+
#define RTC_CR_BCK RTC_CR_BKP
9124+
91139125
/******************** Bits definition for RTC_ISR register ******************/
91149126
#define RTC_ISR_RECALPF_Pos (16U)
91159127
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

‎system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h‎

Lines changed: 24 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32f302xc.h
44
* @author MCD Application Team
5-
* @version V2.3.1
6-
* @date 16-December-2016
75
* @brief CMSIS STM32F302xC Devices Peripheral Access Layer Header File.
86
*
97
* This file contains:
@@ -7343,9 +7341,15 @@ typedef struct
73437341
#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
73447342
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
73457343

7344+
#if defined(EXTI_IMR2_MR33)
73467345
#define EXTI_IMR2_IM_Pos (0U)
73477346
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
73487347
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
7348+
#else
7349+
#define EXTI_IMR2_IM_Pos (0U)
7350+
#define EXTI_IMR2_IM_Msk (0xDU << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */
7351+
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
7352+
#endif
73497353

73507354
/******************* Bit definition for EXTI_EMR2 ****************************/
73517355
#define EXTI_EMR2_MR32_Pos (0U)
@@ -7366,6 +7370,16 @@ typedef struct
73667370
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
73677371
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
73687372

7373+
#if defined(EXTI_EMR2_MR33)
7374+
#define EXTI_EMR2_EM_Pos (0U)
7375+
#define EXTI_EMR2_EM_Msk (0xFU << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */
7376+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
7377+
#else
7378+
#define EXTI_EMR2_EM_Pos (0U)
7379+
#define EXTI_EMR2_EM_Msk (0xDU << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */
7380+
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
7381+
#endif
7382+
73697383
/****************** Bit definition for EXTI_RTSR2 register ********************/
73707384
#define EXTI_RTSR2_TR32_Pos (0U)
73717385
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
@@ -9295,9 +9309,9 @@ typedef struct
92959309
#define RTC_CR_COSEL_Pos (19U)
92969310
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
92979311
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
9298-
#define RTC_CR_BCK_Pos (18U)
9299-
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
9300-
#define RTC_CR_BCK RTC_CR_BCK_Msk
9312+
#define RTC_CR_BKP_Pos (18U)
9313+
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
9314+
#define RTC_CR_BKP RTC_CR_BKP_Msk
93019315
#define RTC_CR_SUB1H_Pos (17U)
93029316
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
93039317
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
@@ -9347,6 +9361,11 @@ typedef struct
93479361
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
93489362
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
93499363

9364+
/* Legacy defines */
9365+
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
9366+
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
9367+
#define RTC_CR_BCK RTC_CR_BKP
9368+
93509369
/******************** Bits definition for RTC_ISR register ******************/
93519370
#define RTC_ISR_RECALPF_Pos (16U)
93529371
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */

0 commit comments

Comments
 (0)