forked from pulp-platform/uvm-components
-
Notifications
You must be signed in to change notification settings - Fork 0
/
core_tb.sv
289 lines (247 loc) · 12 KB
/
core_tb.sv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba, ETH Zurich
// Date: 15/04/2017
// Description: Top level testbench module. Instantiates the top level DUT, configures
// the virtual interfaces and starts the test passed by +UVM_TEST+
import ariane_pkg::*;
import uvm_pkg::*;
import core_lib_pkg::*;
import core_env_pkg::core_test_util;
`timescale 1ns / 1ps
`define DRAM_BASE 64'h40000000
`include "uvm_macros.svh"
module core_tb;
import "DPI-C" function chandle read_elf(string fn);
import "DPI-C" function longint unsigned get_section_address(string symb);
import "DPI-C" function longint unsigned get_section_size(string symb);
import "DPI-C" function longint unsigned get_symbol_address(string symb);
static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
localparam int unsigned CLOCK_PERIOD = 20ns;
logic clk_i;
logic rst_ni;
logic [63:0] time_i;
logic display_instr;
longint unsigned cycles;
longint unsigned max_cycles;
debug_if debug_if();
core_if core_if (clk_i);
dcache_if ptw (clk_i);
dcache_if load_unit (clk_i);
mem_if store_unit (clk_i);
logic [63:0] instr_if_address;
logic instr_if_data_req;
logic instr_if_data_gnt;
logic instr_if_data_rvalid;
logic [63:0] instr_if_data_rdata;
logic [63:0] data_if_data_address_i;
logic [63:0] data_if_data_wdata_i;
logic data_if_data_req_i;
logic data_if_data_we_i;
logic [7:0] data_if_data_be_i;
logic data_if_data_gnt_o;
logic data_if_data_rvalid_o;
logic [63:0] data_if_data_rdata_o;
core_mem core_mem_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.data_if_address_i ( data_if_data_address_i ),
.data_if_data_wdata_i ( data_if_data_wdata_i ),
.data_if_data_req_i ( data_if_data_req_i ),
.data_if_data_we_i ( data_if_data_we_i ),
.data_if_data_be_i ( data_if_data_be_i ),
.data_if_data_rvalid_o ( data_if_data_rvalid_o ),
.data_if_data_rdata_o ( data_if_data_rdata_o )
);
AXI_BUS #(
.AXI_ADDR_WIDTH ( 64 ),
.AXI_DATA_WIDTH ( 64 ),
.AXI_ID_WIDTH ( 10 ),
.AXI_USER_WIDTH ( 1 )
) data_if();
AXI_BUS #(
.AXI_ADDR_WIDTH ( 64 ),
.AXI_DATA_WIDTH ( 64 ),
.AXI_ID_WIDTH ( 10 ),
.AXI_USER_WIDTH ( 1 )
) bypass_if();
AXI_BUS #(
.AXI_ADDR_WIDTH ( 64 ),
.AXI_DATA_WIDTH ( 64 ),
.AXI_ID_WIDTH ( 10 ),
.AXI_USER_WIDTH ( 1 )
) instr_if();
AXI_BUS #(
.AXI_ADDR_WIDTH ( 64 ),
.AXI_DATA_WIDTH ( 64 ),
.AXI_ID_WIDTH ( 12 ),
.AXI_USER_WIDTH ( 1 )
) axi2per();
axi2mem #(
.AXI_ID_WIDTH (12),
.AXI_ADDR_WIDTH (64),
.AXI_DATA_WIDTH (64),
.AXI_USER_WIDTH (1)
) i_axi2mem (
.slave ( axi2per ),
.req_o ( data_if_data_req_i ),
.we_o ( data_if_data_we_i ),
.addr_o ( data_if_data_address_i ),
.be_o ( data_if_data_be_i ),
.data_o ( data_if_data_wdata_i ),
.data_i ( data_if_data_rdata_o ),
.*
);
axi_node_intf_wrap #(
.NB_MASTER ( 1 ),
.NB_SLAVE ( 3 ),
.AXI_ADDR_WIDTH ( 64 ),
.AXI_DATA_WIDTH ( 64 ),
.AXI_ID_WIDTH ( 10 ),
.AXI_USER_WIDTH ( 1 )
) i_axi_node (
.clk ( clk_i ),
.rst_n ( rst_ni ),
.test_en_i ( 1'b0 ),
.slave ( '{bypass_if, data_if, instr_if} ),
.master ( '{axi2per} ),
.start_addr_i ( {64'h0} ),
.end_addr_i ( {64'hFFFF_FFFF_FFFF_FFFF} )
);
ariane dut (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.time_i ( time_i ),
.time_irq_i ( 1'b0 ),
.ipi_i ( 1'b0 ),
.test_en_i ( core_if.test_en ),
.fetch_enable_i ( core_if.fetch_enable ),
.boot_addr_i ( core_if.boot_addr ),
.core_id_i ( core_if.core_id ),
.cluster_id_i ( core_if.cluster_id ),
.flush_dcache_ack_o ( ),
.flush_dcache_i ( 1'b0 ),
.instr_if ( instr_if ),
.data_if ( data_if ),
.bypass_if ( bypass_if ),
.irq_i ( {core_if.irq, core_if.irq} ),
.sec_lvl_o ( core_if.sec_lvl ),
.debug_req_i ( ),
.debug_gnt_o ( ),
.debug_rvalid_o ( ),
.debug_addr_i ( ),
.debug_we_i ( ),
.debug_wdata_i ( ),
.debug_rdata_o ( ),
.debug_halted_o ( ),
.debug_halt_i ( ),
.debug_resume_i ( )
);
// connect core store interface
assign store_unit.address = {dut.ex_stage_i.lsu_i.i_store_unit.address_tag_o, dut.ex_stage_i.lsu_i.i_store_unit.address_index_o};
assign store_unit.data_wdata = dut.ex_stage_i.lsu_i.i_store_unit.data_wdata_o;
assign store_unit.data_req = dut.ex_stage_i.lsu_i.i_store_unit.data_req_o;
assign store_unit.data_we = dut.ex_stage_i.lsu_i.i_store_unit.data_we_o;
assign store_unit.data_be = dut.ex_stage_i.lsu_i.i_store_unit.data_be_o;
assign store_unit.data_gnt = dut.ex_stage_i.lsu_i.i_store_unit.data_gnt_i;
assign store_unit.data_rvalid = dut.ex_stage_i.lsu_i.i_store_unit.data_rvalid_i;
assign store_unit.data_rdata = '0;
// connect load interface
assign load_unit.address_index = dut.ex_stage_i.lsu_i.i_load_unit.address_index_o;
assign load_unit.address_tag = dut.ex_stage_i.lsu_i.i_load_unit.address_tag_o;
assign load_unit.data_wdata = dut.ex_stage_i.lsu_i.i_load_unit.data_wdata_o;
assign load_unit.data_we = dut.ex_stage_i.lsu_i.i_load_unit.data_we_o;
assign load_unit.data_req = dut.ex_stage_i.lsu_i.i_load_unit.data_req_o;
assign load_unit.tag_valid = dut.ex_stage_i.lsu_i.i_load_unit.tag_valid_o;
assign load_unit.data_be = dut.ex_stage_i.lsu_i.i_load_unit.data_be_o;
assign load_unit.kill_req = dut.ex_stage_i.lsu_i.i_load_unit.kill_req_o;
assign load_unit.data_rvalid = dut.ex_stage_i.lsu_i.i_load_unit.data_rvalid_i;
assign load_unit.data_rdata = dut.ex_stage_i.lsu_i.i_load_unit.data_rdata_i;
assign load_unit.data_gnt = dut.ex_stage_i.lsu_i.i_load_unit.data_gnt_i;
// connect ptw interface
assign ptw.address_index = dut.ex_stage_i.lsu_i.i_mmu.i_ptw.address_index_o;
assign ptw.address_tag = dut.ex_stage_i.lsu_i.i_mmu.i_ptw.address_tag_o;
assign ptw.data_wdata = dut.ex_stage_i.lsu_i.i_mmu.i_ptw.data_wdata_o;
assign ptw.data_we = dut.ex_stage_i.lsu_i.i_mmu.i_ptw.data_we_o;
assign ptw.data_req = dut.ex_stage_i.lsu_i.i_mmu.i_ptw.data_req_o;
assign ptw.tag_valid = dut.ex_stage_i.lsu_i.i_mmu.i_ptw.tag_valid_o;
assign ptw.data_be = dut.ex_stage_i.lsu_i.i_mmu.i_ptw.data_be_o;
assign ptw.kill_req = dut.ex_stage_i.lsu_i.i_mmu.i_ptw.kill_req_o;
assign ptw.data_rvalid = dut.ex_stage_i.lsu_i.i_mmu.i_ptw.data_rvalid_i;
assign ptw.data_rdata = dut.ex_stage_i.lsu_i.i_mmu.i_ptw.data_rdata_i;
assign ptw.data_gnt = dut.ex_stage_i.lsu_i.i_mmu.i_ptw.data_gnt_i;
// Clock process
initial begin
clk_i = 1'b0;
rst_ni = 1'b0;
repeat(8)
#(CLOCK_PERIOD/2) clk_i = ~clk_i;
rst_ni = 1'b1;
forever begin
#(CLOCK_PERIOD/2) clk_i = 1'b1;
#(CLOCK_PERIOD/2) clk_i = 1'b0;
//if (cycles > max_cycles)
// $fatal(1, "Simulation reached maximum cycle count of %d", max_cycles);
cycles++;
end
end
// Real Time Clock
initial begin
// initialize platform timer
time_i = 64'b0;
// increment timer with a frequency of 32.768 kHz
forever begin
#30.517578us;
time_i++;
end
end
program testbench (core_if core_if, dcache_if load_unit, dcache_if ptw, mem_if mem_if);
longint unsigned begin_signature_address;
longint unsigned tohost_address;
string max_cycle_string;
string file;
core_test_util ctu;
initial begin
ctu = core_test_util::type_id::create("core_test_util");
file = ctu.get_file_name();
void'(ctu.preload_memories(file));
// read elf file (DPI call)
void'(read_elf(file));
// copy double-wordwise from verilog file
for (int i = 0; i < 2**21; i++)
core_mem_i.ram_i.mem[i] = ctu.rmem[i];
uvm_config_db #(virtual core_if)::set(null, "uvm_test_top", "core_if", core_if);
uvm_config_db #(virtual dcache_if)::set(null, "uvm_test_top", "dcache_if", load_unit);
uvm_config_db #(virtual dcache_if)::set(null, "uvm_test_top", "ptw_if", ptw);
uvm_config_db #(virtual mem_if)::set(null, "uvm_test_top", "mem_if", mem_if);
// we are interested in the .tohost ELF symbol in-order to observe end of test signals
tohost_address = get_symbol_address("tohost");
begin_signature_address = get_symbol_address("begin_signature");
uvm_report_info("Program Loader", $sformatf("tohost: %h begin_signature %h\n", tohost_address, begin_signature_address), UVM_LOW);
// pass tohost address to UVM resource DB
uvm_config_db #(longint unsigned)::set(null, "uvm_test_top.m_env.m_eoc", "tohost", tohost_address);
uvm_config_db #(longint unsigned)::set(null, "uvm_test_top.m_env.m_dcache_scoreboard", "dram_base", `DRAM_BASE);
uvm_config_db #(longint unsigned)::set(null, "uvm_test_top.m_env.m_dcache_scoreboard", "begin_signature", ((begin_signature_address -`DRAM_BASE) >> 3));
uvm_config_db #(core_test_util)::set(null, "uvm_test_top.m_env.m_dcache_scoreboard", "memory_file", ctu);
// print the topology
// uvm_top.enable_print_topology = 1;
// get the maximum cycle count the simulation is allowed to run
if (uvcl.get_arg_value("+max-cycles=", max_cycle_string) == 0) begin
max_cycles = {64{1'b1}};
end else begin
max_cycles = max_cycle_string.atoi();
end
// Start UVM test
run_test();
end
endprogram
testbench tb(core_if, load_unit, ptw, store_unit);
endmodule