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Report that IOAPIC IRQ0 is broken under qemu. #323

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todo bot opened this issue Jun 13, 2019 · 1 comment
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Report that IOAPIC IRQ0 is broken under qemu. #323

todo bot opened this issue Jun 13, 2019 · 1 comment
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todo bot commented Jun 13, 2019

Ideally, we'd use IRQ0 for the timer, in order to match what we have with the PIC. Unfortunately, qemu unconditionally redirects irqs on pin0 to pin2.
We should report this upstream bug, and move back to IRQ0 once it is fixed.


// TODO: Report that IOAPIC IRQ0 is broken under qemu.
// BODY: Ideally, we'd use IRQ0 for the timer, in order to match what we have
// BODY: with the PIC. Unfortunately, qemu [unconditionally redirects irqs on
// BODY: pin0 to pin2](https://github.com/qemu/qemu/blob/37560c259d7a0d6aceb96e9d6903ee002f4e5e0c/hw/intc/ioapic.c#L152).
// BODY:
// BODY: We should report this upstream bug, and move back to IRQ0 once it is
// BODY: fixed.
main_timer.set_interrupt_route(2);
// Clear the interrupt state
hpet_instance.enable();


This issue was generated by todo based on a TODO comment in 8012637 when #304 was merged. cc @roblabla.
@todo todo bot assigned roblabla Jun 13, 2019
@todo todo bot added the todo 🗒️ Created by the todo bot label Jun 13, 2019
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IRQ0 isn't broken, IRQ0 simply redirects to IRQ2 (which is indicated by an MADT entry). However, irq2 is broken... #353

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