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[AArch64] Add a few more vector extension tests.
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llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll

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@@ -145,3 +145,60 @@ define <4 x i64> @cfunc4(<4 x i16> %v0) nounwind {
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%r = sext <4 x i16> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <4 x i64> @zext_v4i8_to_v4i64(<4 x i8> %v0) nounwind {
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; CHECK-LABEL: zext_v4i8_to_v4i64:
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; CHECK-NEXT: bic.4h v0, #255, lsl #8
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ushll2.2d v1, v0, #0
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; CHECK-NEXT: ushll.2d v0, v0, #0
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; CHECK-NEXT: ret
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;
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%r = zext <4 x i8> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <4 x i64> @sext_v4i8_to_v4i64(<4 x i8> %v0) nounwind {
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; CHECK-LABEL: sext_v4i8_to_v4i64:
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ushll.2d v1, v0, #0
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; CHECK-NEXT: ushll2.2d v0, v0, #0
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; CHECK-NEXT: shl.2d v0, v0, #56
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; CHECK-NEXT: shl.2d v2, v1, #56
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; CHECK-NEXT: sshr.2d v1, v0, #56
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; CHECK-NEXT: sshr.2d v0, v2, #56
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; CHECK-NEXT: ret
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;
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%r = sext <4 x i8> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <8 x i64> @zext_v8i8_to_v8i64(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: zext_v8i8_to_v8i64:
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; CHECK-NEXT: ushll.8h v0, v0, #0
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; CHECK-NEXT: ushll2.4s v2, v0, #0
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ushll2.2d v3, v2, #0
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; CHECK-NEXT: ushll2.2d v1, v0, #0
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; CHECK-NEXT: ushll.2d v2, v2, #0
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; CHECK-NEXT: ushll.2d v0, v0, #0
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; CHECK-NEXT: ret
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;
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%r = zext <8 x i8> %v0 to <8 x i64>
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ret <8 x i64> %r
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}
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define <8 x i64> @sext_v8i8_to_v8i64(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: sext_v8i8_to_v8i64:
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; CHECK-NEXT: sshll.8h v0, v0, #0
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; CHECK-NEXT: sshll2.4s v2, v0, #0
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; CHECK-NEXT: sshll.4s v0, v0, #0
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; CHECK-NEXT: sshll2.2d v3, v2, #0
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; CHECK-NEXT: sshll2.2d v1, v0, #0
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; CHECK-NEXT: sshll.2d v2, v2, #0
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; CHECK-NEXT: sshll.2d v0, v0, #0
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; CHECK-NEXT: ret
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;
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%r = sext <8 x i8> %v0 to <8 x i64>
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ret <8 x i64> %r
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}

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