Changing the way to treat vector masks

[kaz7]

The current implementation ignores vector masks in VP intrinsics if they won't cause exceptions.

For example, VP_MUL intrinsic instruction with vector mask is converted to VMULSWSX without mask like below. Current implementation uses vector masks for only VP_SDIV/UDIV/FDIV instructions.

define fastcc <256 x i32> @test_vp_int(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_int:
; CHECK:       # %bb.0:
; CHECK-NEXT:    and %s0, %s0, (32)0
; CHECK-NEXT:    lvl %s0
; CHECK-NEXT:    vmuls.w.sx %v0, %v0, %v1
; CHECK-NEXT:    b.l.t (, %s10)
  %r0 = call <256 x i32> @llvm.vp.mul.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
  ret <256 x i32> %r0
}

I'm going to change this to not ignore vector masks even if the instruction won't cause errors. @simoll , please let me know if you have any reason to ignore these vector masks. Thanks.