pipeline8.si

// mockup of multi-fsm pipeline

unit C(input uint8 i,output! uint8 o,output! uint1 last(0))
{
  always_before{ last = 0; }
  algorithm {
    uint8 t(0);
    t = i;
  ++:
    t = t + 1;
  ++:
    t = t + 1;
  ++:
    t = t + 1;
    o = t;
    last = 1;
  }
}

unit B(input uint8 i,output! uint8 o,output! uint1 last(0))
{
  always_before{ last = 0; }
  algorithm {
    uint8 t(0);
    t = i;
  ++:
    t = t + 1;
  ++:
    t = t + 1;
    o = t;
    last = 1;
  }
}

unit A(input uint8 i,output! uint8 o,output! uint1 last(0))
{
  always_before{ last = 0; }
  algorithm {
    uint8 t(0);
    t = i;
  ++:
    t = t + 1;
    o = t;
    last = 1;
  }
}

unit main(output uint8 leds)
{
  uint32 cycle(0);
  A a; B b; C c;

  algorithm {  while (1) {

    {
      // stage 0
      uint1 valid(0);
      uint1 first(1);
      if (a.last | first) {
        // next
        a.i     = cycle;
        first   = 0;
        valid   = 1;
      }
      if (valid & (b.last | isdone(b))) {
        a <- ();
        valid = 0;
        __display("[cycle %d] A (a.i:%d)",cycle,a.i);
        __display("[cycle %d] ==== input :%d",cycle,a.i);
      }

      // check at every cycle
      if (c.last) {
        __display("[cycle %d] ==== result:%d",cycle,c.o);
      }
      cycle vv= cycle + 1;
      //    ^ assigns out of pipeline
      if (cycle == 40) { __finish(); }

    -> // stage 1

      uint1 valid(0);
      if (a.last) {
        // next
        b.i = a.o;
        valid = 1;
      }
      if (valid & (b.last | isdone(b))
                & (c.last | isdone(c))) {
        b <- ();
        valid = 0;
        __display("[cycle %d] B (b.i:%d)",cycle,b.i);
      }

    -> // stage 2

      uint1 valid(0);
      if (b.last) {
        // next
        c.i = b.o;
        valid = 1;
      }
      if (valid & (c.last | isdone(c))) {
        c <- ();
        valid = 0;
        __display("[cycle %d] C (c.i:%d)",cycle,c.i);
      }

    } // end of pipeline

  } }
}