galp5 - 2021-09-20 FW build - boot entries disappearing. #246

ZeddieXX · 2021-09-21T16:06:42Z

I have a GALP5 (iGPU) and on both the 2021-07-20 and 2021-09-20 firmware, the boot entries seem to disappear when I perform a cold boot. I have Pop!_OS 21.04 and Windows 10/11 installed and I perform dual-boot. I also use an Akitio Node TB3 eGPU with an RTX 3070 Ti and USB mouse. It may be related.

crawfxrd · 2021-09-21T16:12:13Z

Does it happen reliably?

Verify the SMMSTORE is being cleared:

make -C coreboot/util/cbmem
sudo ./coreboot/util/cbmem/cbmem -c | grep "CMOS reset"

If you can, after every boot (need it before and after boot entries disappear), dump the CMOS to see what values changed:

make -C coreboot/util/nvramtool
sudo ./coreboot/util/nvramtool -a
sudo ./coreboot/util/nvramtool -x

stnley · 2021-10-03T22:01:42Z

Just wanted to +1. I experience the same phenomenon on both FW versions. The only OS which has stayed reliably is Ubuntu 20.04. I don't have the expertise to debug but I'll try the steps provided by @crawfxrd

ZeddieXX · 2021-10-16T03:36:13Z

Sorry, I just don't have that much time to troubleshoot this issue, but today I had some time to look into this. Very first line gave me an error:
zeddie@galp5:~/temp/firmware-open$ make -C coreboot/util/cbmem
make: *** coreboot/util/cbmem: No such file or directory. Stop.

Sure enough, there is nothing inside the coreboot directory. I did a new git clone https://github.com/system76/firmware-open/

jacobgkau · 2021-10-18T14:27:24Z

there is nothing inside the coreboot directory. I did a new git clone

Did you run the scripts/update.sh script or run git submodule update --init --recursive?

ZeddieXX · 2021-10-18T18:20:39Z

there is nothing inside the coreboot directory. I did a new git clone

Did you run the scripts/update.sh script or run git submodule update --init --recursive?

No, but I'll give it a try now. I just reinstalled Windows and Pop!_OS 21.04. I may not be using my eGPU anymore (cable is bad, not very stable, more trouble than it's worth), but what I've noticed is that soemtimes when I have a device in the USB port on the left side (USB-A or the USB-C), the laptop doesn't respond to the ESC key to go into the boot menu. I noticed this when I was reinstalling the OSes.

Also, when this happens, the boot entries get cleared. Even after a clean install of both OSes, Windows Boot Manager is now gone.

I'm not sure why this is happening, and it's frustrating.

I want to reiterate: I'm not a developer or coder. My knowledge goes as far as Windows batch files, and barely just learning bash script (just to automate some things). I'm not all that familiar with git. If you need me to do something, please give me a step-by-step. I will eventually learn as I go along, but I wanted to set expectations.

ZeddieXX · 2021-10-18T18:38:49Z

After running
make -C coreboot/util/nvramtool

I ran the next line
sudo ./coreboot/util/nvramtool -a

I get command not found.

jacobgkau · 2021-10-18T21:24:24Z

I ran the next line
sudo ./coreboot/util/nvramtool -a

I get command not found.

It looks like those two last lines should be ./coreboot/util/nvramtool/nvramtool (with the options from each line). After making, there will be an nvramtool file inside of the nvramtool directory.

ZeddieXX · 2021-10-18T22:53:45Z

I'm actually trying this:
https://support.system76.com/articles/open-firmware-smmstore

I removed the NVME drive and flashed this firmware via a USB drive. I then updated to the current available firmware (2021-07-20). I'm going to reinstall the OSes again and see if this fixes the issue.

Would using Ventoy be an issue? I don't think it should, but figured I'd ask anyways.

Update: it didn't work. After installing PopOS, then, Windows 11 (Win11 install.wim in Win 10 ISO to avoid restrictions), boot entries are gone.

I'm getting really frustrated with this. :(

ZeddieXX · 2021-10-19T06:05:24Z

I ran the next line
sudo ./coreboot/util/nvramtool -a
I get command not found.

It looks like those two last lines should be ./coreboot/util/nvramtool/nvramtool (with the options from each line). After making, there will be an nvramtool file inside of the nvramtool directory.

I'll give this a try when I can gather the energy to try again.

ZeddieXX · 2021-10-19T12:52:28Z

You said to run it before and after if I can. I'm assuming only running the last two lines before and after, right? Because after "make", the toil is already compiled so no need to recompile again for the after?

make -C coreboot/util/nvramtool
sudo ./coreboot/util/nvramtool -a <--- This
sudo ./coreboot/util/nvramtool -x <--- and this

Before boot entries disappear (ex: after running bootrec /fixmbr and whatever the Linux version of the fix bootloader command for system-d?) And then after?

jacobgkau · 2021-10-19T14:25:17Z

I'm actually trying this:
https://support.system76.com/articles/open-firmware-smmstore

That support article is for a very specific issue and should not be used here.

You said to run it before and after if I can. I'm assuming only running the last two lines before and after, right? Because after "make", the toil is already compiled so no need to recompile again for the after?

That should be correct, although running the make command just shouldn't do anything if nothing needs to be done.

ZeddieXX · 2021-10-23T18:40:17Z

I don't remember how to recreate the Linux boot loader, but I did add the Windows one at least. Here I confirm it shows up in efibootmgr, then I ran the two commands. After this, I'm going to reboot and run the commands again after confirming the boot entry is gone.

zeddie@zedlin-galp5:~/temp/firmware-open$ efibootmgr
BootCurrent: 0001
Timeout: 2 seconds
BootOrder: 0004,0000,0001
Boot0000* UiApp
Boot0001* WDC WDS500G2B0C-00PXH0
Boot0004* Windows Boot Manager

zeddie@zedlin-galp5:~/temp/firmware-open$ sudo coreboot/util/nvramtool/nvramtool -a
boot_option = Fallback
reboot_counter = 0x0
preserve_smmstore = 0x1

zeddie@zedlin-galp5:~/temp/firmware-open$ sudo coreboot/util/nvramtool/nvramtool -x
0000 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0010 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0020 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0030 | 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0040 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0050 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0060 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0070 | 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 | ................
0080 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0090 | 1c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00a0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00b0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00c0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 aa 55 | ...............U
00d0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff ff | ................
00e0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00f0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................

ZeddieXX · 2021-10-23T18:43:29Z

After a reboot, Windows Boot Manager is gone.

zeddie@zedlin-galp5:~$ efibootmgr
BootCurrent: 0001
Timeout: 2 seconds
BootOrder: 0000,0001
Boot0000* UiApp
Boot0001* WDC WDS500G2B0C-00PXH0

zeddie@zedlin-galp5:~/temp/firmware-open$ sudo coreboot/util/nvramtool/nvramtool -a
[sudo] password for zeddie:
boot_option = Fallback
reboot_counter = 0x0
preserve_smmstore = 0x1

zeddie@zedlin-galp5:~/temp/firmware-open$ sudo coreboot/util/nvramtool/nvramtool -x
0000 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0010 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0020 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0030 | 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0040 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0050 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0060 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0070 | 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 | ................
0080 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0090 | 1c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00a0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00b0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00c0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 aa 55 | ...............U
00d0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff ff | ................
00e0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00f0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................

ZeddieXX · 2021-10-23T18:49:47Z

Oh, and there were no outputs for:
zeddie@zedlin-galp5:~/temp/firmware-open$ sudo coreboot/util/cbmem/cbmem -c | grep "CMOS reset"

Sorry it took a while. Busy life. I'm having less time to play and troubleshoot, so now I just need a laptop that works. Been using my work-issued laptop since I couldn't reliably get this to dual-boot.

So what do I do now?

crawfxrd · 2021-10-23T20:19:32Z

I can create a firmware update image that dumps the CMOS NVRAM to the cbmem console. Then if you check the cbmem console, you will see hex dump of the actual values, and not what coreboot rewrites.

sudo ./coreboot/util/cbmem/cbmem -c > cbmem.txt

Optionally, I could change the default behavior to not clear the SMMSTORE. You would have to be careful about the SMMSTORE used space, as this could trigger #145 again. Unfortunately there's no convenient way to check this right now, but I can update one of the tools to report the used space, along with if it detects the region is corrupted.

galp5-76ec.zip

Build: 2021-10-23_dfc8d23 [1]
This build logs the CMOS values to cbmem console before coreboot rewrites them [2].
It does not disable clearing the SMMSTORE.

Instructions for using this are here: #145 (comment)

ZeddieXX · 2021-10-24T04:25:26Z

I flashed the firmware you gave me and ran the command. Here you go:

`

coreboot-2021-10-23_dfc8d23 Sat Oct 23 21:06:11 UTC 2021 bootblock starting (log level: 7)...
CPU: 11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHz
CPU: ID 806c1, Tigerlake B0, ucode: 00000086
CPU: AES supported, TXT NOT supported, VT supported
MCH: device id 9a14 (rev 01) is Tigerlake-U-4-2
PCH: device id a082 (rev 20) is Tigerlake-U Premium SKU
IGD: device id 9a49 (rev 01) is Tigerlake U GT2
system76: DGPU power 1
FMAP: Found "FLASH" version 1.1 at 0x650000.
FMAP: base = 0xff000000 size = 0x1000000 #areas = 5
FMAP: area COREBOOT found @ 650200 (10157568 bytes)
CBFS: mcache @0xfef42600 built for 16 files, used 0x390 of 0x2000 bytes
CBFS: Found 'fallback/romstage' @0x80 size 0x1012c in mcache @0xfef42638
BS: bootblock times (exec / console): total (unknown) / 0 ms

coreboot-2021-10-23_dfc8d23 Sat Oct 23 21:06:11 UTC 2021 romstage starting (log level: 0)...
pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00001c00
gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
TCO_STS: 0000 0000
GEN_PMCON: d0015038 00002200
GBLRST_CAUSE: 00000000 00000000
HPR_CAUSE0: 00000000
prev_sleep_state 5
CBFS: Found 'fspm.bin' @0x4bdc0 size 0x9f000 in mcache @0xfef4285c
POST: 0x34
FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
SPD: module type is DDR4
SPD: module part number is KHX3200C20S4/16G
SPD: banks 16, ranks 1, rows 17, columns 10, density 16384 Mb
SPD: device width 8 bits, bus width 64 bits
SPD: module size is 16384 MB (per channel)
SPD: module type is DDR4
SPD: module part number is KHX3200C20S4/16G
SPD: banks 16, ranks 1, rows 17, columns 10, density 16384 Mb
SPD: device width 8 bits, bus width 64 bits
SPD: module size is 16384 MB (per channel)
POST: 0x36
POST: 0x92
POST: 0x98
CBMEM:
IMD: root @ 0x76fff000 254 entries.
IMD: root @ 0x76ffec00 62 entries.
FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes)
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
MRC: updated 'RW_MRC_CACHE'.
2 DIMMs found
SMM Memory Map
SMRAM : 0x7b800000 0x800000
Subregion 0: 0x7b800000 0x200000
Subregion 1: 0x7ba00000 0x200000
Subregion 2: 0x7bc00000 0x400000
top_of_ram = 0x77000000
MTRR Range: Start=76000000 End=77000000 (Size 1000000)
MTRR Range: Start=7b800000 End=7c000000 (Size 800000)
MTRR Range: Start=ff000000 End=0 (Size 1000000)
CBFS: Found 'fallback/postcar' @0x12d980 size 0x48a8 in mcache @0xfef428dc
Decompressing stage fallback/postcar @ 0x76c21fc0 (35200 bytes)
Loading module at 0x76c22000 with entry 0x76c22031. filesize: 0x45d0 memsize: 0x8940
Processing 159 relocs. Offset value of 0x74c22000
BS: romstage times (exec / console): total (unknown) / 1 ms

coreboot-2021-10-23_dfc8d23 Sat Oct 23 21:06:11 UTC 2021 postcar starting (log level: 0)...
CBFS: Found 'fallback/ramstage' @0x2aac0 size 0x1a0a7 in mcache @0x76c4d0ec
Decompressing stage fallback/ramstage @ 0x76bc3fc0 (379024 bytes)
Loading module at 0x76bc4000 with entry 0x76bc4000. filesize: 0x3a780 memsize: 0x5c850
Processing 3974 relocs. Offset value of 0x75dc4000
BS: postcar times (exec / console): total (unknown) / 0 ms

coreboot-2021-10-23_dfc8d23 Sat Oct 23 21:06:11 UTC 2021 ramstage starting (log level: 0)...
POST: 0x39
POST: 0x80
POST: 0x70
CBFS: Found 'cpu_microcode_blob.bin' @0x10240 size 0x1a800 in mcache @0x76c4d09c
microcode: sig=0x806c1 pf=0x80 revision=0x86
microcode: Update skipped, already up-to-date
CBFS: Found 'fsps.bin' @0xebdc0 size 0x41b73 in mcache @0x76c4d29c
Detected 4 core, 8 thread CPU.
Setting up SMI for CPU
IED base = 0x7bc00000
IED size = 0x00400000
Will perform SMM setup.
CPU: 11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHz.
Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
Processing 16 relocs. Offset value of 0x00030000
Attempting to start 7 APs
Waiting for 10ms after sending INIT.
Waiting for 1st SIPI to complete...done.
AP: slot 1 apic_id 1.
Waiting for 2nd SIPI to complete...done.
AP: slot 2 apic_id 5.
AP: slot 3 apic_id 4.
AP: slot 4 apic_id 3.
AP: slot 5 apic_id 2.
AP: slot 6 apic_id 7.
AP: slot 7 apic_id 6.
Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
Processing 13 relocs. Offset value of 0x00038000
SMM Module: stub loaded at 0x00038000. Will call 0x76bdccc5(0x00000000)
Installing permanent SMM handler to 0x7b800000
Loading module at 0x7b810000 with entry 0x7b810cc9. filesize: 0x37c8 memsize: 0x7908
Processing 190 relocs. Offset value of 0x7b810000
Loading module at 0x7b808000 with entry 0x7b808000. filesize: 0x1b8 memsize: 0x1b8
Processing 13 relocs. Offset value of 0x7b808000
SMM Module: placing jmp sequence at 0x7b807c00 rel16 0x03fd
SMM Module: placing jmp sequence at 0x7b807800 rel16 0x07fd
SMM Module: placing jmp sequence at 0x7b807400 rel16 0x0bfd
SMM Module: placing jmp sequence at 0x7b807000 rel16 0x0ffd
SMM Module: placing jmp sequence at 0x7b806c00 rel16 0x13fd
SMM Module: placing jmp sequence at 0x7b806800 rel16 0x17fd
SMM Module: placing jmp sequence at 0x7b806400 rel16 0x1bfd
SMM Module: stub loaded at 0x7b808000. Will call 0x7b810cc9(0x00000000)
Clearing SMI status registers
SMI_STS: PM1
TMROF smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b800000, cpu = 0
In relocation handler: CPU 0
New SMBASE=0x7b800000 IEDBASE=0x7bc00000
Writing SMRR. base = 0x7b800006, mask=0xff800c00
Relocation complete.
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b7ffc00, cpu = 1
In relocation handler: CPU 1
New SMBASE=0x7b7ffc00 IEDBASE=0x7bc00000
Relocation complete.
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b7ff400, cpu = 3
In relocation handler: CPU 3
New SMBASE=0x7b7ff400 IEDBASE=0x7bc00000
Writing SMRR. base = 0x7b800006, mask=0xff800c00
Relocation complete.
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b7ff800, cpu = 2
In relocation handler: CPU 2
New SMBASE=0x7b7ff800 IEDBASE=0x7bc00000
Relocation complete.
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b7ff000, cpu = 4
In relocation handler: CPU 4
New SMBASE=0x7b7ff000 IEDBASE=0x7bc00000
Relocation complete.
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b7fe800, cpu = 6
In relocation handler: CPU 6
New SMBASE=0x7b7fe800 IEDBASE=0x7bc00000
Relocation complete.
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b7fe400, cpu = 7
In relocation handler: CPU 7
New SMBASE=0x7b7fe400 IEDBASE=0x7bc00000
Writing SMRR. base = 0x7b800006, mask=0xff800c00
Relocation complete.
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b7fec00, cpu = 5
In relocation handler: CPU 5
New SMBASE=0x7b7fec00 IEDBASE=0x7bc00000
Writing SMRR. base = 0x7b800006, mask=0xff800c00
Relocation complete.
Initializing CPU #0
CPU: vendor Intel device 806c1
CPU: family 06, model 8c, stepping 01
Clearing out pending MCEs
Setting up local APIC...
apic_id: 0x00 done.
Turbo is available but hidden
Turbo is available and visible
microcode: Update skipped, already up-to-date
CPU #0 initialized
Initializing CPU #1
Initializing CPU #2
Initializing CPU #3
Initializing CPU #6
CPU: vendor Intel device 806c1
CPU: family 06, model 8c, stepping 01
CPU: vendor Intel device 806c1
CPU: family 06, model 8c, stepping 01
Clearing out pending MCEs
Clearing out pending MCEs
CPU: vendor Intel device 806c1
CPU: family 06, model 8c, stepping 01
Initializing CPU #4
Initializing CPU #5
CPU: vendor Intel device 806c1
CPU: family 06, model 8c, stepping 01
CPU: vendor Intel device 806c1
CPU: family 06, model 8c, stepping 01
Clearing out pending MCEs
Clearing out pending MCEs
CPU: vendor Intel device 806c1
CPU: family 06, model 8c, stepping 01
Initializing CPU #7
Clearing out pending MCEs
CPU: vendor Intel device 806c1
CPU: family 06, model 8c, stepping 01
Clearing out pending MCEs
Clearing out pending MCEs
Setting up local APIC...
Setting up local APIC...
Setting up local APIC...
Setting up local APIC...
Setting up local APIC...
Setting up local APIC...
Setting up local APIC...
apic_id: 0x04 done.
apic_id: 0x03 done.
apic_id: 0x07 done.
apic_id: 0x05 done.
apic_id: 0x02 done.
apic_id: 0x06 done.
microcode: Update skipped, already up-to-date
CPU #3 initialized
microcode: Update skipped, already up-to-date
CPU #2 initialized
microcode: Update skipped, already up-to-date
CPU #4 initialized
microcode: Update skipped, already up-to-date
CPU #6 initialized
microcode: Update skipped, already up-to-date
CPU #5 initialized
apic_id: 0x01 done.
microcode: Update skipped, already up-to-date
CPU #7 initialized
microcode: Update skipped, already up-to-date
CPU #1 initialized
bsp_do_flight_plan done after 4 msecs.
CPU: frequency set to 4700 MHz
Enabling SMIs.
BS: BS_DEV_INIT_CHIPS entry times (exec / console): 63 / 1 ms
POST: 0x71
CBFS: Found 'vbt.bin' @0x4b140 size 0x51c in mcache @0x76c4d1d4
Found a VBT of 8704 bytes after decompression
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
POST: 0x93
FSPS returned 0
POST: 0x99
POST: 0xa0
FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
Detected 4 core, 8 thread CPU.
Detected 4 core, 8 thread CPU.
POST: 0xa1
Display FSP Version Info HOB
Reference Code - CPU = a.0.37.41
uCode Version = 0.0.0.86
TXT ACM version = ff.ff.ff.ffff
Reference Code - ME = a.0.37.41
MEBx version = 0.0.0.0
ME Firmware Version = Consumer SKU
Reference Code - PCH = a.0.37.41
PCH-CRID Status = Disabled
PCH-CRID Original Value = ff.ff.ff.ffff
PCH-CRID New Value = ff.ff.ff.ffff
OPROM - RST - RAID = ff.ff.ff.ffff
PCH Hsio Version = 4.0.0.0
Reference Code - SA - System Agent = a.0.37.41
Reference Code - MRC = 1.0.a.2
SA - PCIe Version = a.0.37.41
SA-CRID Status = Disabled
SA-CRID Original Value = 0.0.0.1
SA-CRID New Value = 0.0.0.1
OPROM - VBIOS = ff.ff.ff.ffff
IO Manageability Engine FW Version = 11.1.1.0
PHY Build Version = 0.0.0.f6
Thunderbolt(TM) FW Version = 24.1.0.0
System Agent Manageability Engine FW Version = ff.ff.ff.ffff
ITSS IRQ Polarities Before:
IPC0: 0xffffffff
IPC1: 0xffffffff
IPC2: 0xffffffff
IPC3: 0xffffffff
ITSS IRQ Polarities After:
IPC0: 0xffffffff
IPC1: 0xffffffff
IPC2: 0xffffffff
IPC3: 0xffffffff
Found PCIe Root Port #9 at PCI: 00:1d.0.
Found PCIe Root Port #10 at PCI: 00:1d.1.
pcie_rp_update_dev: Couldn't find PCIe Root Port #5 (originally PCI: 00:1c.4) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
BS: BS_DEV_INIT_CHIPS run times (exec / console): 1832 / 0 ms
POST: 0x72
Enumerating buses...
Root Device scanning...
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:00.0 [8086/9a14] enabled
PCI: 00:02.0 [8086/9a49] enabled
PCI: 00:04.0 [8086/9a03] enabled
PCI: 00:06.0 subordinate bus PCI Express
PCI: 00:06.0 [8086/9a09] enabled
PCI: 00:07.0 subordinate bus PCI Express
PCI: 00:07.0 hot-plug capable
PCI: 00:07.0 [8086/9a23] enabled
PCI: 00:08.0 [8086/9a11] enabled
PCI: 00:0a.0 [8086/9a0d] disabled
PCI: 00:0d.0 [8086/9a13] enabled
PCI: 00:0d.2 [8086/9a1b] enabled
PCI: 00:14.0 [8086/a0ed] enabled
PCI: 00:14.2 [8086/a0ef] enabled
PCI: 00:14.3 [8086/a0f0] enabled
PCI: 00:15.0 [8086/a0e8] enabled
PCI: 00:15.1 [8086/a0e9] enabled
PCI: 00:15.2 [8086/a0ea] enabled
PCI: 00:16.0 [8086/a0e0] enabled
PCI: 00:19.0 [8086/a0c5] disabled
PCI: 00:19.2 [8086/a0c7] enabled
PCI: 00:1d.0 [8086/a0b0] enabled
PCI: 00:1d.1 [8086/a0b1] enabled
PCI: 00:1f.0 [8086/a082] enabled
PCI: Static device PCI: 00:1f.1 not found, disabling it.
RTC Init
CMOS NVRAM:
0000 | 58 00 21 00 04 00 07 24 10 21 26 02 50 80 00 00
0010 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0020 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0030 | 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00
0040 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0050 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0060 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0070 | 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00
0080 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0090 | 1C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00A0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00B0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00C0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 AA 55
00D0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FF FF
00E0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00F0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
No CMOS option 'power_on_after_fail'.
Set power on after power failure.
Disabling Deep S3
Disabling Deep S3
Disabling Deep S4
Disabling Deep S4
Disabling Deep S5
Disabling Deep S5
PCI: 00:1f.2 [0000/0000] hidden
PCI: 00:1f.3 [8086/a0c8] enabled
PCI: 00:1f.4 [8086/a0a3] enabled
PCI: 00:1f.5 [8086/a0a4] enabled
POST: 0x25
GPIO: 0 enabled
PCI: Leftover static devices:
PCI: 00:10.2
PCI: 00:10.6
PCI: 00:10.7
PCI: 00:05.0
PCI: 00:07.1
PCI: 00:07.2
PCI: 00:07.3
PCI: 00:09.0
PCI: 00:0d.1
PCI: 00:0d.3
PCI: 00:0e.0
PCI: 00:12.0
PCI: 00:12.6
PCI: 00:13.0
PCI: 00:14.1
PCI: 00:15.3
PCI: 00:16.1
PCI: 00:16.2
PCI: 00:16.3
PCI: 00:16.4
PCI: 00:16.5
PCI: 00:17.0
PCI: 00:19.1
PCI: 00:1e.0
PCI: 00:1e.1
PCI: 00:1e.2
PCI: 00:1e.3
PCI: 00:1f.1
PCI: 00:1f.6
PCI: 00:1f.7
PCI: Check your devicetree.cb.
PCI: 00:02.0 scanning...
scan_bus: bus PCI: 00:02.0 finished in 0 msecs
PCI: 00:04.0 scanning...
scan_bus: bus PCI: 00:04.0 finished in 0 msecs
PCI: 00:06.0 scanning...
PCI: pci_scan_bus for bus 01
POST: 0x24
PCI: 01:00.0 [15b7/5009] enabled
POST: 0x25
POST: 0x55
Enabling Common Clock Configuration
L1 Sub-State supported from root port 6
L1 Sub-State Support = 0x5
CommonModeRestoreTime = 0x2d
Power On Value = 0x5, Power On Scale = 0x1
ASPM: Enabled L1
PCIe: Max_Payload_Size adjusted to 256
scan_bus: bus PCI: 00:06.0 finished in 0 msecs
PCI: 00:07.0 scanning...
PCI: pci_scan_bus for bus 02
POST: 0x24
POST: 0x25
GENERIC: 0.0 enabled
POST: 0x55
scan_bus: bus PCI: 00:07.0 finished in 0 msecs
PCI: 00:0d.0 scanning...
USB0 port 0 enabled
USB0 port 0 scanning...
USB3 port 0 enabled
USB3 port 1 disabled
USB3 port 2 disabled
USB3 port 3 disabled
USB3 port 0 scanning...
scan_bus: bus USB3 port 0 finished in 0 msecs
scan_bus: bus USB0 port 0 finished in 0 msecs
scan_bus: bus PCI: 00:0d.0 finished in 0 msecs
PCI: 00:0d.2 scanning...
GENERIC: 0.0 enabled
bus: PCI: 00:0d.2[0]->scan_bus: bus PCI: 00:0d.2 finished in 0 msecs
PCI: 00:14.0 scanning...
USB0 port 0 enabled
USB0 port 0 scanning...
USB2 port 0 enabled
USB2 port 1 enabled
USB2 port 2 enabled
USB2 port 3 disabled
USB2 port 4 enabled
USB2 port 5 enabled
USB2 port 6 enabled
USB2 port 7 disabled
USB2 port 8 disabled
USB2 port 9 enabled
USB3 port 0 enabled
USB3 port 1 enabled
USB3 port 2 enabled
USB3 port 3 enabled
USB2 port 0 scanning...
scan_bus: bus USB2 port 0 finished in 0 msecs
USB2 port 1 scanning...
scan_bus: bus USB2 port 1 finished in 0 msecs
USB2 port 2 scanning...
scan_bus: bus USB2 port 2 finished in 0 msecs
USB2 port 4 scanning...
scan_bus: bus USB2 port 4 finished in 0 msecs
USB2 port 5 scanning...
scan_bus: bus USB2 port 5 finished in 0 msecs
USB2 port 6 scanning...
scan_bus: bus USB2 port 6 finished in 0 msecs
USB2 port 9 scanning...
scan_bus: bus USB2 port 9 finished in 0 msecs
USB3 port 0 scanning...
scan_bus: bus USB3 port 0 finished in 0 msecs
USB3 port 1 scanning...
scan_bus: bus USB3 port 1 finished in 0 msecs
USB3 port 2 scanning...
scan_bus: bus USB3 port 2 finished in 0 msecs
USB3 port 3 scanning...
scan_bus: bus USB3 port 3 finished in 0 msecs
scan_bus: bus USB0 port 0 finished in 0 msecs
scan_bus: bus PCI: 00:14.0 finished in 0 msecs
PCI: 00:14.3 scanning...
GENERIC: 0.0 enabled
scan_bus: bus PCI: 00:14.3 finished in 0 msecs
PCI: 00:15.0 scanning...
I2C: 00:38 enabled
scan_bus: bus PCI: 00:15.0 finished in 0 msecs
PCI: 00:15.1 scanning...
scan_bus: bus PCI: 00:15.1 finished in 0 msecs
PCI: 00:15.2 scanning...
scan_bus: bus PCI: 00:15.2 finished in 0 msecs
PCI: 00:1d.0 scanning...
PCI: pci_scan_bus for bus 23
POST: 0x24
PCI: 23:00.0 [10ec/522a] enabled
POST: 0x25
POST: 0x55
Enabling Common Clock Configuration
L1 Sub-State supported from root port 29
L1 Sub-State Support = 0xf
CommonModeRestoreTime = 0x3c
Power On Value = 0x6, Power On Scale = 0x1
ASPM: Enabled L0s and L1
PCIe: Max_Payload_Size adjusted to 128
scan_bus: bus PCI: 00:1d.0 finished in 0 msecs
PCI: 00:1d.1 scanning...
PCI: pci_scan_bus for bus 24
POST: 0x24
PCI: 24:00.0 [10ec/8168] enabled
POST: 0x25
GENERIC: 0.0 enabled
POST: 0x55
Enabling Common Clock Configuration
L1 Sub-State supported from root port 29
L1 Sub-State Support = 0xf
CommonModeRestoreTime = 0x96
Power On Value = 0xf, Power On Scale = 0x1
ASPM: Enabled L1
PCIe: Max_Payload_Size adjusted to 128
scan_bus: bus PCI: 00:1d.1 finished in 0 msecs
PCI: 00:1f.0 scanning...
PNP: 0c31.0 enabled
scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
PCI: 00:1f.2 scanning...
GENERIC: 0.0 enabled
GENERIC: 0.0 scanning...
GENERIC: 0.0 enabled
scan_bus: bus GENERIC: 0.0 finished in 0 msecs
scan_bus: bus PCI: 00:1f.2 finished in 0 msecs
PCI: 00:1f.3 scanning...
scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
PCI: 00:1f.4 scanning...
scan_bus: bus PCI: 00:1f.4 finished in 0 msecs
PCI: 00:1f.5 scanning...
scan_bus: bus PCI: 00:1f.5 finished in 0 msecs
POST: 0x55
scan_bus: bus DOMAIN: 0000 finished in 8 msecs
scan_bus: bus Root Device finished in 8 msecs
done
BS: BS_DEV_ENUMERATE run times (exec / console): 8 / 0 ms
MRC: Could not find region 'UNIFIED_MRC_CACHE'
FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes)
MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
system76: failed to find PEGP
POST: 0x73
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Done reading resources.
==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:06.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
PCI: 01:00.0 20 * [0x4000 - 0x40ff] mem
PCI: 00:06.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:07.0 io: size: 0 align: 12 gran: 12 limit: ffff
NONE 18 * [0x0 - 0x1fff] io
PCI: 00:07.0 io: size: 2000 align: 12 gran: 12 limit: ffff done
PCI: 00:07.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
NONE 10 * [0x0 - 0x1ffffff] mem
PCI: 00:07.0 mem: size: 2000000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:07.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
NONE 14 * [0x0 - 0x1fffffff] prefmem
PCI: 00:07.0 prefmem: size: 20000000 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 23:00.0 10 * [0x0 - 0xfff] mem
PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1d.1 io: size: 0 align: 12 gran: 12 limit: ffff
PCI: 24:00.0 10 * [0x0 - 0xff] io
PCI: 00:1d.1 io: size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1d.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 24:00.0 20 * [0x0 - 0x3fff] mem
PCI: 24:00.0 18 * [0x4000 - 0x4fff] mem
PCI: 00:1d.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1d.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1d.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
=== Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
update_constraints: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
DOMAIN: 0000: Resource ranges:

Base: 1000, Size: 800, Tag: 100
Base: 1900, Size: d6a0, Tag: 100
Base: efc0, Size: 1040, Tag: 100
PCI: 00:07.0 1c * [0x2000 - 0x3fff] limit: 3fff io
PCI: 00:1d.1 1c * [0x4000 - 0x4fff] limit: 4fff io
PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
update_constraints: PCI: 00:00.0 0f base 77000000 limit 803fffff mem (fixed)
update_constraints: PCI: 00:00.0 10 base 100000000 limit 87fbfffff mem (fixed)
update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
update_constraints: PCI: 00:19.2 10 base fe03e000 limit fe03efff mem (fixed)
update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
DOMAIN: 0000: Resource ranges:
Base: 80400000, Size: 3fc00000, Tag: 200
Base: d0000000, Size: 28000000, Tag: 200
Base: fa000000, Size: 1000000, Tag: 200
Base: fb001000, Size: 2fff000, Tag: 200
Base: fe010000, Size: 2e000, Tag: 200
Base: fe03f000, Size: d01000, Tag: 200
Base: fed45000, Size: 3b000, Tag: 200
Base: fed88000, Size: 8000, Tag: 200
Base: fed93000, Size: d000, Tag: 200
Base: feda2000, Size: 1e000, Tag: 200
Base: fede0000, Size: 1220000, Tag: 200
Base: 87fc00000, Size: 7780400000, Tag: 100200
PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
PCI: 00:02.0 10 * [0x81000000 - 0x81ffffff] limit: 81ffffff mem
PCI: 00:07.0 24 * [0xa0000000 - 0xbfffffff] limit: bfffffff prefmem
PCI: 00:07.0 20 * [0x82000000 - 0x83ffffff] limit: 83ffffff mem
PCI: 00:06.0 20 * [0x80400000 - 0x804fffff] limit: 804fffff mem
PCI: 00:1d.0 20 * [0x80500000 - 0x805fffff] limit: 805fffff mem
PCI: 00:1d.1 20 * [0x80600000 - 0x806fffff] limit: 806fffff mem
PCI: 00:1f.3 20 * [0x80700000 - 0x807fffff] limit: 807fffff mem
PCI: 00:0d.2 10 * [0x80800000 - 0x8083ffff] limit: 8083ffff mem
PCI: 00:04.0 10 * [0x80840000 - 0x8085ffff] limit: 8085ffff mem
PCI: 00:0d.0 10 * [0x80860000 - 0x8086ffff] limit: 8086ffff mem
PCI: 00:14.0 10 * [0x80870000 - 0x8087ffff] limit: 8087ffff mem
PCI: 00:14.2 10 * [0x80880000 - 0x80883fff] limit: 80883fff mem
PCI: 00:14.3 10 * [0x80884000 - 0x80887fff] limit: 80887fff mem
PCI: 00:1f.3 10 * [0x80888000 - 0x8088bfff] limit: 8088bfff mem
PCI: 00:08.0 10 * [0x8088c000 - 0x8088cfff] limit: 8088cfff mem
PCI: 00:0d.2 18 * [0x8088d000 - 0x8088dfff] limit: 8088dfff mem
PCI: 00:14.2 18 * [0x8088e000 - 0x8088efff] limit: 8088efff mem
PCI: 00:15.0 10 * [0x8088f000 - 0x8088ffff] limit: 8088ffff mem
PCI: 00:15.1 10 * [0x80890000 - 0x80890fff] limit: 80890fff mem
PCI: 00:15.2 10 * [0x80891000 - 0x80891fff] limit: 80891fff mem
PCI: 00:16.0 10 * [0x80892000 - 0x80892fff] limit: 80892fff mem
PCI: 00:19.2 18 * [0x80893000 - 0x80893fff] limit: 80893fff mem
PCI: 00:1f.5 10 * [0x80894000 - 0x80894fff] limit: 80894fff mem
PCI: 00:1f.4 10 * [0x80895000 - 0x808950ff] limit: 808950ff mem
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
PCI: 00:06.0 mem: base: 80400000 size: 100000 align: 20 gran: 20 limit: 804fffff
PCI: 00:06.0: Resource ranges:
Base: 80400000, Size: 100000, Tag: 200
PCI: 01:00.0 10 * [0x80400000 - 0x80403fff] limit: 80403fff mem
PCI: 01:00.0 20 * [0x80404000 - 0x804040ff] limit: 804040ff mem
PCI: 00:06.0 mem: base: 80400000 size: 100000 align: 20 gran: 20 limit: 804fffff done
PCI: 00:07.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff
PCI: 00:07.0: Resource ranges:
Base: 2000, Size: 2000, Tag: 100
NONE 18 * [0x2000 - 0x3fff] limit: 3fff io
PCI: 00:07.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff done
PCI: 00:07.0 prefmem: base: a0000000 size: 20000000 align: 20 gran: 20 limit: bfffffff
PCI: 00:07.0: Resource ranges:
Base: a0000000, Size: 20000000, Tag: 1200
NONE 14 * [0xa0000000 - 0xbfffffff] limit: bfffffff prefmem
PCI: 00:07.0 prefmem: base: a0000000 size: 20000000 align: 20 gran: 20 limit: bfffffff done
PCI: 00:07.0 mem: base: 82000000 size: 2000000 align: 20 gran: 20 limit: 83ffffff
PCI: 00:07.0: Resource ranges:
Base: 82000000, Size: 2000000, Tag: 200
NONE 10 * [0x82000000 - 0x83ffffff] limit: 83ffffff mem
PCI: 00:07.0 mem: base: 82000000 size: 2000000 align: 20 gran: 20 limit: 83ffffff done
PCI: 00:1d.0 mem: base: 80500000 size: 100000 align: 20 gran: 20 limit: 805fffff
PCI: 00:1d.0: Resource ranges:
Base: 80500000, Size: 100000, Tag: 200
PCI: 23:00.0 10 * [0x80500000 - 0x80500fff] limit: 80500fff mem
PCI: 00:1d.0 mem: base: 80500000 size: 100000 align: 20 gran: 20 limit: 805fffff done
PCI: 00:1d.1 io: base: 4000 size: 1000 align: 12 gran: 12 limit: 4fff
PCI: 00:1d.1: Resource ranges:
Base: 4000, Size: 1000, Tag: 100
PCI: 24:00.0 10 * [0x4000 - 0x40ff] limit: 40ff io
PCI: 00:1d.1 io: base: 4000 size: 1000 align: 12 gran: 12 limit: 4fff done
PCI: 00:1d.1 mem: base: 80600000 size: 100000 align: 20 gran: 20 limit: 806fffff
PCI: 00:1d.1: Resource ranges:
Base: 80600000, Size: 100000, Tag: 200
PCI: 24:00.0 20 * [0x80600000 - 0x80603fff] limit: 80603fff mem
PCI: 24:00.0 18 * [0x80604000 - 0x80604fff] limit: 80604fff mem
PCI: 00:1d.1 mem: base: 80600000 size: 100000 align: 20 gran: 20 limit: 806fffff done
=== Resource allocator: DOMAIN: 0000 - resource allocation complete ===
PCI: 00:02.0 10 <- [0x0081000000 - 0x0081ffffff] size 0x01000000 gran 0x18 mem64
PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
PCI: 00:04.0 10 <- [0x0080840000 - 0x008085ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:06.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:06.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:06.0 20 <- [0x0080400000 - 0x00804fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 01:00.0 10 <- [0x0080400000 - 0x0080403fff] size 0x00004000 gran 0x0e mem64
PCI: 01:00.0 20 <- [0x0080404000 - 0x00804040ff] size 0x00000100 gran 0x08 mem64
PCI: 00:07.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 02 io
PCI: 00:07.0 24 <- [0x00a0000000 - 0x00bfffffff] size 0x20000000 gran 0x14 bus 02 prefmem
PCI: 00:07.0 20 <- [0x0082000000 - 0x0083ffffff] size 0x02000000 gran 0x14 bus 02 mem
NONE missing set_resources
PCI: 00:08.0 10 <- [0x008088c000 - 0x008088cfff] size 0x00001000 gran 0x0c mem64
PCI: 00:0d.0 10 <- [0x0080860000 - 0x008086ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:0d.2 10 <- [0x0080800000 - 0x008083ffff] size 0x00040000 gran 0x12 mem64
PCI: 00:0d.2 18 <- [0x008088d000 - 0x008088dfff] size 0x00001000 gran 0x0c mem64
PCI: 00:14.0 10 <- [0x0080870000 - 0x008087ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:14.2 10 <- [0x0080880000 - 0x0080883fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.2 18 <- [0x008088e000 - 0x008088efff] size 0x00001000 gran 0x0c mem64
PCI: 00:14.3 10 <- [0x0080884000 - 0x0080887fff] size 0x00004000 gran 0x0e mem64
PCI: 00:15.0 10 <- [0x008088f000 - 0x008088ffff] size 0x00001000 gran 0x0c mem64
PCI: 00:15.1 10 <- [0x0080890000 - 0x0080890fff] size 0x00001000 gran 0x0c mem64
PCI: 00:15.2 10 <- [0x0080891000 - 0x0080891fff] size 0x00001000 gran 0x0c mem64
PCI: 00:16.0 10 <- [0x0080892000 - 0x0080892fff] size 0x00001000 gran 0x0c mem64
PCI: 00:19.2 18 <- [0x0080893000 - 0x0080893fff] size 0x00001000 gran 0x0c mem64
PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 23 io
PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 23 prefmem
PCI: 00:1d.0 20 <- [0x0080500000 - 0x00805fffff] size 0x00100000 gran 0x14 bus 23 mem
PCI: 23:00.0 10 <- [0x0080500000 - 0x0080500fff] size 0x00001000 gran 0x0c mem
PCI: 00:1d.1 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 24 io
PCI: 00:1d.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 24 prefmem
PCI: 00:1d.1 20 <- [0x0080600000 - 0x00806fffff] size 0x00100000 gran 0x14 bus 24 mem
PCI: 24:00.0 10 <- [0x0000004000 - 0x00000040ff] size 0x00000100 gran 0x08 io
PCI: 24:00.0 18 <- [0x0080604000 - 0x0080604fff] size 0x00001000 gran 0x0c mem64
PCI: 24:00.0 20 <- [0x0080600000 - 0x0080603fff] size 0x00004000 gran 0x0e mem64
LPC: Cannot open window to resource fed40000 size 5000
LPC: MMIO window already in use
PCI: 00:1f.3 10 <- [0x0080888000 - 0x008088bfff] size 0x00004000 gran 0x0e mem64
PCI: 00:1f.3 20 <- [0x0080700000 - 0x00807fffff] size 0x00100000 gran 0x14 mem64
PCI: 00:1f.4 10 <- [0x0080895000 - 0x00808950ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.5 10 <- [0x0080894000 - 0x0080894fff] size 0x00001000 gran 0x0c mem
Done setting resources.
Done allocating resources.
BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms
POST: 0x94
POST: 0x94
POST: 0x74
Enabling resources...
PCI: 00:00.0 subsystem <- 1558/4018
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 1558/4018
PCI: 00:02.0 cmd <- 03
PCI: 00:04.0 subsystem <- 1558/4018
PCI: 00:04.0 cmd <- 02
PCI: 00:06.0 bridge ctrl <- 0013
PCI: 00:06.0 cmd <- 06
PCI: 00:07.0 bridge ctrl <- 0013
PCI: 00:07.0 cmd <- 07
PCI: 00:08.0 subsystem <- 1558/4018
PCI: 00:08.0 cmd <- 06
PCI: 00:0d.0 subsystem <- 1558/4018
PCI: 00:0d.0 cmd <- 02
PCI: 00:0d.2 subsystem <- 1558/4018
PCI: 00:0d.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1558/4018
PCI: 00:14.0 cmd <- 02
PCI: 00:14.2 subsystem <- 1558/4018
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1558/4018
PCI: 00:14.3 cmd <- 02
PCI: 00:15.0 subsystem <- 1558/4018
PCI: 00:15.0 cmd <- 02
PCI: 00:15.1 subsystem <- 1558/4018
PCI: 00:15.1 cmd <- 02
PCI: 00:15.2 subsystem <- 1558/4018
PCI: 00:15.2 cmd <- 02
PCI: 00:16.0 subsystem <- 1558/4018
PCI: 00:16.0 cmd <- 02
PCI: 00:19.2 subsystem <- 1558/4018
PCI: 00:19.2 cmd <- 06
PCI: 00:1d.0 bridge ctrl <- 0013
PCI: 00:1d.0 subsystem <- 1558/4018
PCI: 00:1d.0 cmd <- 06
PCI: 00:1d.1 bridge ctrl <- 0013
PCI: 00:1d.1 subsystem <- 1558/4018
PCI: 00:1d.1 cmd <- 07
PCI: 00:1f.0 subsystem <- 1558/4018
PCI: 00:1f.0 cmd <- 407
PCI: 00:1f.3 subsystem <- 1558/4018
PCI: 00:1f.3 cmd <- 02
PCI: 00:1f.4 subsystem <- 1558/4018
PCI: 00:1f.4 cmd <- 03
PCI: 00:1f.5 subsystem <- 1558/4018
PCI: 00:1f.5 cmd <- 406
PCI: 01:00.0 cmd <- 02
PCI: 23:00.0 cmd <- 02
PCI: 24:00.0 cmd <- 03
done.
Found TPM SLB9670 TT 2.0 by Infineon
tlcl_send_startup: Startup return code is 0
TPM: setup succeeded
BS: BS_DEV_INIT entry times (exec / console): 12 / 0 ms
POST: 0x75
Initializing devices...
POST: 0x75
POST: 0x75
POST: 0x75
PCI: 00:00.0 init
CPU TDP = 28 Watts
CPU PL1 = 28 Watts
CPU PL2 = 51 Watts
PCI: 00:00.0 init finished in 1 msecs
POST: 0x75
PCI: 00:02.0 init
GMA: Found VBT in CBFS
GMA: Found valid VBT in CBFS
framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
x_res x y_res: 1920 x 1080, size: 8294400 at 0x90000000
PCI: 00:02.0 init finished in 0 msecs
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
PCI: 00:08.0 init
PCI: 00:08.0 init finished in 0 msecs
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
PCI: 00:14.0 init
PCI: 00:14.0 init finished in 0 msecs
POST: 0x75
PCI: 00:14.2 init
PCI: 00:14.2 init finished in 0 msecs
POST: 0x75
POST: 0x75
PCI: 00:15.0 init
I2C bus 0 version 0x3230302a
DW I2C bus 0 at 0x8088f000 (400 KHz)
PCI: 00:15.0 init finished in 0 msecs
POST: 0x75
PCI: 00:15.1 init
I2C bus 1 version 0x3230302a
DW I2C bus 1 at 0x80890000 (400 KHz)
PCI: 00:15.1 init finished in 0 msecs
POST: 0x75
PCI: 00:15.2 init
I2C bus 2 version 0x3230302a
DW I2C bus 2 at 0x80891000 (400 KHz)
PCI: 00:15.2 init finished in 0 msecs
POST: 0x75
PCI: 00:16.0 init
PCI: 00:16.0 init finished in 0 msecs
POST: 0x75
POST: 0x75
POST: 0x75
PCI: 00:1d.0 init
Initializing PCH PCIe bridge.
PCI: 00:1d.0 init finished in 0 msecs
POST: 0x75
PCI: 00:1d.1 init
Initializing PCH PCIe bridge.
PCI: 00:1d.1 init finished in 0 msecs
POST: 0x75
PCI: 00:1f.0 init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
PCI: 00:1f.0 init finished in 0 msecs
POST: 0x75
PCI: 00:1f.2 init
Disabling ACPI via APMC.
APMC done.
PCI: 00:1f.2 init finished in 0 msecs
POST: 0x75
PCI: 00:1f.3 init
HDA: codec_mask = 05
HDA: Initializing codec Trouble compiling serde #2
HDA: codec viddid: 80862812
HDA: No verb table entry found
HDA: Initializing codec #0
HDA: codec viddid: 10ec0293
HDA: verb loaded.
PCI: 00:1f.3 init finished in 5 msecs
POST: 0x75
PCI: 00:1f.4 init
PCI: 00:1f.4 init finished in 0 msecs
POST: 0x75
POST: 0x75
PCI: 01:00.0 init
PCI: 01:00.0 init finished in 0 msecs
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
PCI: 23:00.0 init
PCI: 23:00.0 init finished in 0 msecs
POST: 0x75
POST: 0x75
PCI: 24:00.0 init
PCI: 24:00.0 init finished in 0 msecs
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
Devices initialized
BS: BS_DEV_INIT run times (exec / console): 7 / 0 ms
POST: 0x76
Finalize devices...
Devices finalized
POST: 0x77
ME: HFSTS1 : 0x90000055
ME: HFSTS2 : 0x60000116
ME: HFSTS3 : 0x00000020
ME: HFSTS4 : 0x00004000
ME: HFSTS5 : 0x00000000
ME: HFSTS6 : 0x00400000
ME: Manufacturing Mode : YES
ME: SPI Protection Mode Enabled : NO
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : NO
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: D0i3 Support : YES
ME: Low Power State Enabled : NO
ME: CPU Replaced : YES
ME: CPU Replacement Valid : YES
ME: Current Working State : 5
ME: Current Operation State : 1
ME: Current Operation Mode : 0
ME: Error Code : 0
ME: Enhanced Debug Mode : NO
ME: CPU Debug Disabled : NO
ME: TXT Support : NO
POST: 0x79
POST: 0x9c
CBFS: Found 'fallback/dsdt.aml' @0x45400 size 0x5cd2 in mcache @0x76c4d19c
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 76b37000.
ACPI: * FACS
ACPI: * DSDT
PCI space above 4GB MMIO is at 0x87fc00000, len = 0x7780400000
ACPI: * FADT
SCI is IRQ9
ACPI: added table 1/32, length now 40
ACPI: * SSDT
Found 1 CPU(s) with 4/8 physical/logical core(s) each.
PSS: 2801MHz power 28000 control 0x2f00 status 0x2f00
PSS: 2800MHz power 28000 control 0x1c00 status 0x1c00
PSS: 2400MHz power 22892 control 0x1800 status 0x1800
PSS: 2000MHz power 18212 control 0x1400 status 0x1400
PSS: 1600MHz power 13877 control 0x1000 status 0x1000
PSS: 1200MHz power 9898 control 0xc00 status 0xc00
PSS: 800MHz power 6264 control 0x800 status 0x800
PSS: 400MHz power 2962 control 0x400 status 0x400
PSS: 2801MHz power 28000 control 0x2f00 status 0x2f00
PSS: 2800MHz power 28000 control 0x1c00 status 0x1c00
PSS: 2400MHz power 22892 control 0x1800 status 0x1800
PSS: 2000MHz power 18212 control 0x1400 status 0x1400
PSS: 1600MHz power 13877 control 0x1000 status 0x1000
PSS: 1200MHz power 9898 control 0xc00 status 0xc00
PSS: 800MHz power 6264 control 0x800 status 0x800
PSS: 400MHz power 2962 control 0x400 status 0x400
PSS: 2801MHz power 28000 control 0x2f00 status 0x2f00
PSS: 2800MHz power 28000 control 0x1c00 status 0x1c00
PSS: 2400MHz power 22892 control 0x1800 status 0x1800
PSS: 2000MHz power 18212 control 0x1400 status 0x1400
PSS: 1600MHz power 13877 control 0x1000 status 0x1000
PSS: 1200MHz power 9898 control 0xc00 status 0xc00
PSS: 800MHz power 6264 control 0x800 status 0x800
PSS: 400MHz power 2962 control 0x400 status 0x400
PSS: 2801MHz power 28000 control 0x2f00 status 0x2f00
PSS: 2800MHz power 28000 control 0x1c00 status 0x1c00
PSS: 2400MHz power 22892 control 0x1800 status 0x1800
PSS: 2000MHz power 18212 control 0x1400 status 0x1400
PSS: 1600MHz power 13877 control 0x1000 status 0x1000
PSS: 1200MHz power 9898 control 0xc00 status 0xc00
PSS: 800MHz power 6264 control 0x800 status 0x800
PSS: 400MHz power 2962 control 0x400 status 0x400
PSS: 2801MHz power 28000 control 0x2f00 status 0x2f00
PSS: 2800MHz power 28000 control 0x1c00 status 0x1c00
PSS: 2400MHz power 22892 control 0x1800 status 0x1800
PSS: 2000MHz power 18212 control 0x1400 status 0x1400
PSS: 1600MHz power 13877 control 0x1000 status 0x1000
PSS: 1200MHz power 9898 control 0xc00 status 0xc00
PSS: 800MHz power 6264 control 0x800 status 0x800
PSS: 400MHz power 2962 control 0x400 status 0x400
PSS: 2801MHz power 28000 control 0x2f00 status 0x2f00
PSS: 2800MHz power 28000 control 0x1c00 status 0x1c00
PSS: 2400MHz power 22892 control 0x1800 status 0x1800
PSS: 2000MHz power 18212 control 0x1400 status 0x1400
PSS: 1600MHz power 13877 control 0x1000 status 0x1000
PSS: 1200MHz power 9898 control 0xc00 status 0xc00
PSS: 800MHz power 6264 control 0x800 status 0x800
PSS: 400MHz power 2962 control 0x400 status 0x400
PSS: 2801MHz power 28000 control 0x2f00 status 0x2f00
PSS: 2800MHz power 28000 control 0x1c00 status 0x1c00
PSS: 2400MHz power 22892 control 0x1800 status 0x1800
PSS: 2000MHz power 18212 control 0x1400 status 0x1400
PSS: 1600MHz power 13877 control 0x1000 status 0x1000
PSS: 1200MHz power 9898 control 0xc00 status 0xc00
PSS: 800MHz power 6264 control 0x800 status 0x800
PSS: 400MHz power 2962 control 0x400 status 0x400
PSS: 2801MHz power 28000 control 0x2f00 status 0x2f00
PSS: 2800MHz power 28000 control 0x1c00 status 0x1c00
PSS: 2400MHz power 22892 control 0x1800 status 0x1800
PSS: 2000MHz power 18212 control 0x1400 status 0x1400
PSS: 1600MHz power 13877 control 0x1000 status 0x1000
PSS: 1200MHz power 9898 control 0xc00 status 0xc00
PSS: 800MHz power 6264 control 0x800 status 0x800
PSS: 400MHz power 2962 control 0x400 status 0x400
_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
_SB.PCI0.TRP0: Intel USB4 PCIe Root Port at PCI: 00:07.0
: Intel USB4 Retimer at GENERIC: 0.0
_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
_SB.PCI0.I2C0.H038: FocalTech Touchpad at I2C: 00:38
_SB.PCI0.RP10: Enable RTD3 for PCI: 00:1d.1 (Intel PCIe Runtime D3) on RP Darter: External bootable M.2 USB enclosure is not bootable #10
_SB.PCI0.LPCB.TPM.TPM: LPC TPM PNP: 0c31.0
_SB.PCI0.TXHC.RHUB.SS01: USB3 J_TYPEC2 at USB3 port 0
_SB.PCI0.XHCI.RHUB.HS01: USB2 J_USB3_2 at USB2 port 0
_SB.PCI0.XHCI.RHUB.HS02: USB2 J_TYPEC1 at USB2 port 1
_SB.PCI0.XHCI.RHUB.HS03: USB2 J_USB3_1 at USB2 port 2
_SB.PCI0.XHCI.RHUB.HS05: USB2 Fingerprint at USB2 port 4
_SB.PCI0.XHCI.RHUB.HS06: USB2 J_TYPEC2 at USB2 port 5
_SB.PCI0.XHCI.RHUB.HS07: USB2 Camera at USB2 port 6
_SB.PCI0.XHCI.RHUB.HS10: USB2 Bluetooth at USB2 port 9
_SB.PCI0.XHCI.RHUB.SS01: USB3 J_USB3_2 at USB3 port 0
_SB.PCI0.XHCI.RHUB.SS02: USB3 J_TYPEC1 CH0 at USB3 port 1
_SB.PCI0.XHCI.RHUB.SS03: USB3 J_USB3_1 at USB3 port 2
_SB.PCI0.XHCI.RHUB.SS04: USB3 J_TYPEC1 CH1 at USB3 port 3
_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: added table 3/32, length now 48
ACPI: * TPM2
TPM2 log created at 0x76b27000
ACPI: added table 4/32, length now 52
ACPI: * LPIT
ACPI: added table 5/32, length now 56
ACPI: * MADT
SCI is IRQ9
ACPI: added table 6/32, length now 60
current = 76b3f4a0
ACPI: * DMAR
ACPI: added table 7/32, length now 64
ACPI: added table 8/32, length now 68
ACPI: * HPET
ACPI: added table 9/32, length now 72
ACPI: done.
ACPI tables: 34272 bytes.
smbios_write_tables: 76b26000
SMBIOS firmware version is set to coreboot_version: '2021-10-23_dfc8d23'
Create SMBIOS type 16
Create SMBIOS type 17
GENERIC: 0.0 (WIFI Device)
SMBIOS tables: 867 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum d928
Writing coreboot table at 0x76b5b000
CBFS: Found 'cmos_layout.bin' @0x4b800 size 0x2b8 in mcache @0x76c4d234

0000000000000000-0000000000000fff: CONFIGURATION TABLES
0000000000001000-000000000009ffff: RAM
00000000000a0000-00000000000fffff: RESERVED
0000000000100000-0000000076b25fff: RAM
0000000076b26000-0000000076bc3fff: CONFIGURATION TABLES
0000000076bc4000-0000000076c20fff: RAMSTAGE
0000000076c21000-0000000076ffffff: CONFIGURATION TABLES
0000000077000000-00000000803fffff: RESERVED
00000000c0000000-00000000cfffffff: RESERVED
00000000f8000000-00000000f9ffffff: RESERVED
00000000fb000000-00000000fb000fff: RESERVED
00000000fe000000-00000000fe00ffff: RESERVED
00000000fed40000-00000000fed44fff: RESERVED
00000000fed80000-00000000fed87fff: RESERVED
00000000fed90000-00000000fed92fff: RESERVED
00000000feda0000-00000000feda1fff: RESERVED
00000000fedc0000-00000000feddffff: RESERVED
0000000100000000-000000087fbfffff: RAM
SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
Wrote coreboot table at: 0x76b5b000, 0x788 bytes, checksum c8b
coreboot table: 1952 bytes.
IMD ROOT 0. 0x76fff000 0x00001000
IMD SMALL 1. 0x76ffe000 0x00001000
FSP MEMORY 2. 0x76c4e000 0x003b0000
RO MCACHE 3. 0x76c4d000 0x00000390
CONSOLE 4. 0x76c2d000 0x00020000
TIME STAMP 5. 0x76c2c000 0x00000910
ROMSTG STCK 6. 0x76c2b000 0x00001000
AFTER CAR 7. 0x76c21000 0x0000a000
RAMSTAGE 8. 0x76bc3000 0x0005e000
ACPI GNVS 9. 0x76bc2000 0x00001000
REFCODE 10. 0x76b68000 0x0005a000
4f444749 11. 0x76b66000 0x00002000
EXT VBT12. 0x76b63000 0x0000217b
COREBOOT 13. 0x76b5b000 0x00008000
ACPI 14. 0x76b37000 0x00024000
TPM2 TCGLOG15. 0x76b27000 0x00010000
SMBIOS 16. 0x76b26000 0x00000800
IMD small region:
IMD ROOT 0. 0x76ffec00 0x00000400
FSP RUNTIME 1. 0x76ffebe0 0x00000004
FMAP 2. 0x76ffeac0 0x0000010a
POWER STATE 3. 0x76ffea60 0x00000044
ROMSTAGE 4. 0x76ffea40 0x00000004
MEM INFO 5. 0x76ffe860 0x000001e0
BS: BS_WRITE_TABLES run times (exec / console): 3 / 0 ms
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
0x0000000077000000 - 0x0000000090000000 size 0x19000000 type 0
0x0000000090000000 - 0x00000000a0000000 size 0x10000000 type 1
0x00000000a0000000 - 0x0000000100000000 size 0x60000000 type 0
0x0000000100000000 - 0x000000087fc00000 size 0x77fc00000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
CPU physical address size: 39 bits
MTRR: default type WB/UC MTRR counts: 6/8.
MTRR: WB selected as default type.
MTRR: 0 base 0x0000000077000000 mask 0x0000007fff000000 type 0
MTRR: 1 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
MTRR: 2 base 0x0000000080000000 mask 0x0000007ff0000000 type 0
MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 1
MTRR: 4 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0

MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled

POST: 0x93
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
BS: BS_WRITE_TABLES exit times (exec / console): 6 / 0 ms
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
CPU physical address size: 39 bits
POST: 0x7a
CPU physical address size: 39 bits
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
CPU physical address size: 39 bits
CPU physical address size: 39 bits
CPU physical address size: 39 bits
CPU physical address size: 39 bits
CPU physical address size: 39 bits
CBFS: Found 'fallback/payload' @0x132280 size 0xc12f6 in mcache @0x76c4d314
Checking segment from ROM address 0xff7824b8
Checking segment from ROM address 0xff7824d4
Loading segment from ROM address 0xff7824b8
code (compression=1)
New segment dstaddr 0x00800000 memsize 0x800000 srcaddr 0xff7824f0 filesize 0xc12be
Loading Segment: addr: 0x00800000 memsz: 0x0000000000800000 filesz: 0x00000000000c12be
using LZMA
Loading segment from ROM address 0xff7824d4
Entry Point 0x00800860
BS: BS_PAYLOAD_LOAD run times (exec / console): 714 / 0 ms
POST: 0x95
POST: 0x95
POST: 0x88
POST: 0x89
Finalizing chipset.
Finalizing SMM.
APMC done.
POST: 0xfe
BS: BS_PAYLOAD_LOAD exit times (exec / console): 69 / 0 ms
POST: 0x7b
mp_park_aps done after 0 msecs.
Jumping to boot code at 0x00800860(0x76b5b000)
POST: 0xf8
`

ZeddieXX · 2021-10-24T04:32:19Z

So help me understand. Before the issue was the SMMSTORE was not clearing boot entries, so it gets full and it can't be rewritten? And now the CMOS is clearing the SMMSTORE every time it boots? I think we need a better solution.

crawfxrd · 2021-10-24T05:19:41Z

Did you have the issue on this boot? You will need to reproduce the issue and boot to Linux. The full cbmem console log isn't needed, just the hex dump at CMOS NVRAM:.

So help me understand. Before the issue was the SMMSTORE was not clearing boot entries, so it gets full and it can't be rewritten?

Yes. SMMSTOREv1 is append-only, so at a certain point it would just run out of space and fail to do any operations involving EFI variables.

And now the CMOS is clearing the SMMSTORE every time it boots?

Not every time. As a workaround to the previous issue, we added an option that would allow users to reset the CMOS battery in order to erase SMMSTORE. The problem is we don't know what else writes to CMOS, or where: Earlier it was Windows writing the ALT_CENTURY byte.

I think we need a better solution.

We have it: SMMSTOREv2. It supports read-modify-write and fault tolerate writes. It will allow us to remove the CMOS hack, and these issues should almost never happen again. (The caveat is that if the firmware volume does somehow become corrupted, it will erase it to get back to a known good state.)

I have #260 to track remaining work needed for the next firmware update.

stnley · 2021-10-24T05:40:02Z

I just was able to reproduce this again. Freshly installed Arch, shutdown multiple times over the course of a few hours. Every time it booted into grub fine, except this latest instance when it dropped into grub shell.

I dumped the CMOS right after I booted into Arch for the first time:

boot_option = Fallback
reboot_counter = 0x0
preserve_smmstore = 0x1
0000 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0010 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0020 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0030 | 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0040 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0050 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0060 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0070 | 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 | ................
0080 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0090 | 1c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00a0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00b0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00c0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 aa 55 | ...............U
00d0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 6f | ...............o
00e0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00f0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................

This is the dump after booting from grub shell:

boot_option = Fallback
reboot_counter = 0x0
preserve_smmstore = 0x1
0000 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0010 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0020 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0030 | 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0040 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0050 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0060 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0070 | 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 | ................
0080 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
0090 | 1c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00a0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00b0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00c0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 aa 55 | ...............U
00d0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 6f | ...............o
00e0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................
00f0 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................

Oddly, it looks identical to me. If my experience is unrelated let me know.

ZeddieXX · 2021-10-24T22:46:07Z

Did you have the issue on this boot? You will need to reproduce the issue and boot to Linux. The full cbmem console log isn't needed, just the hex dump at CMOS NVRAM:.

Yes I did have the issue on this boot.

I think we need a better solution.

We have it: SMMSTOREv2. It supports read-modify-write and fault tolerate writes. It will allow us to remove the CMOS hack, and these issues should almost never happen again. (The caveat is that if the firmware volume does somehow become corrupted, it will erase it to get back to a known good state.)

I have #260 to track remaining work needed for the next firmware update.

That's good news. Do you know how long before it is released into the standard firmware update feed? Or is this something we need to compile and flash manually?

crawfxrd · 2021-10-26T02:31:46Z

Yes I did have the issue on this boot.

Then the fact that the cbmem dump matches the nvramtool dump, and the lack of the "CMOS reset" log, implies it's not the preserve_smmstore CMOS option causing it.

The only other, seemingly very unlikely, cause I can think of is firmware-smmstore. But for that to happen it would have to:

Detect more at 50% space used or more the 16 duplicate EFI vars (on every boot you have the issue)
Successfully erase the region
And then fail to write anything back

That's good news. Do you know how long before it is released into the standard firmware update feed? Or is this something we need to compile and flash manually?

The tasks in the tracking issues need to be completed, and then any issues that come up in testing, so it may be some time before its released.

pipipi314 · 2021-10-26T20:46:41Z

I just want to say that I have the same issue with galp5. Also some reports on youtube with the same issue: https://www.youtube.com/watch?v=e47Tq90fHqc

I install debian 11 on a new disk (UEFI). After the first successful boot to the installed OS, on the next reboot the boot entries are missing.

If I boot from recovery USB, and "reinstall grub", I can boot again, but only once. On the second reboot, boot entries are missing.

It is not happening for the original drive and original OS(popos)

Please let me know if you need more info

ZeddieXX · 2021-10-28T01:28:55Z

I just want to say that I have the same issue with galp5. Also some reports on youtube with the same issue: https://www.youtube.com/watch?v=e47Tq90fHqc

I install debian 11 on a new disk (UEFI). After the first successful boot to the installed OS, on the next reboot the boot entries are missing.

If I boot from recovery USB, and "reinstall grub", I can boot again, but only once. On the second reboot, boot entries are missing.

It is not happening for the original drive and original OS(popos)

Please let me know if you need more info

That's my video! :)

pipipi314 · 2021-10-29T00:04:45Z

Just flashed a build from #260
~~The boot entries are missing ...~~

Actually it is slightly different. I can see the boot options in "One Time Boot", but it wont allow me to boot, the message I
get is:

SecureBoot is disabled.
Booting from 'NVME ...' failed; verify it contains a 64-bit UEFI OS

Press any key to continue booting ...

crawfxrd · 2021-10-29T00:08:08Z

How did you flash it?

pipipi314 · 2021-10-29T00:09:13Z

with libs/intel-spi/target/release/intel-spi ... if that was your question about

pipipi314 · 2021-10-29T00:10:15Z

How do I disable SecureBoot?

crawfxrd · 2021-10-29T00:13:52Z

SMMSTORE is not copied when using intel-spi or a CH341A programmer, so boot entries will always be lost if flashing via scripts/flash.sh or scripts/ch341a-flash.sh.

firmware-update doesn't migrate data to the new format yet, so it will actually always get erased right now.

crawfxrd · 2021-10-29T00:17:48Z

You didn't have to configure anything for that to happen? Right now, I expect it to boot into Setup Mode with Secure Boot disabled.

pipipi314 · 2021-10-29T00:19:48Z

I didn't configure anything. I just cloned the repo, checkout the-one-big, git submodule update, then ./scripts/deps.sh then ./scrpts/buld.sh galp5.
then I flashed it with intel-spi

crawfxrd · 2021-10-29T00:21:34Z

Secure Boot is not configurable from the firmware yet. You will have to build and flash with SECURE_BOOT_ENABLE=FALSE. This can be set by creating a file called models/<model>/edk2.config with that config. (See models/oryp8/edk2.config as an example.)

crawfxrd self-assigned this Oct 20, 2021

crawfxrd mentioned this issue Oct 28, 2021

The big one #260

Merged

28 tasks

crawfxrd linked a pull request Nov 10, 2021 that will close this issue

The big one #260

Merged

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crawfxrd closed this as completed in #260 Dec 21, 2021

crawfxrd mentioned this issue Jul 30, 2022

New releases for all models #340

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galp5 - 2021-09-20 FW build - boot entries disappearing. #246

galp5 - 2021-09-20 FW build - boot entries disappearing. #246

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galp5 - 2021-09-20 FW build - boot entries disappearing. #246

galp5 - 2021-09-20 FW build - boot entries disappearing. #246

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