The "examples" folder contains example designs for specific FPGA development kits.
This README gives a brief description of each example design.
Target: Xilinx AC701 standalone design
Loopback SGMII testing for Xilinx AC701, using the built-in SMA ports. Provides metrics for signal-integrity testing.
Target: Xilinx AC701 + Custom I/O board
A family of example designs for the Xilinx AC701 dev-kit coupled to a custom FMC I/O board. The I/O board includes an Ethernet switch ASIC, PMOD ports for Ethernet-over-SPI/UART, and gigabit Ethernet PHYs. Variants are provided using RMII, RGMII, and SGMII interfaces.
Target: Xilinx AC701 + Avnet Network FMC
This design hosts a three-port IPv4 router on the AC701, using an off-the-shelf FMC card with two additional Ethernet PHYs (RGMII). It also showcases the use of SatCat5 IP-core wrappers in the Vivado block diagram tool.
Target: Digilent Arty A7-35T or A7-100T
This design hosts a SatCat5 Ethernet switch that connects the Arty's built-in RJ45 port to the four PMOD ports. Each PMOD port acts as an auto-sensing Ethernet-over-SPI/UART port.
Target: Digilent Arty A7-35T or A7-100T
This design is similar to "arty_a7", but with a managed SatCat5 Ethernet switch and a built-in Microblaze processor. It also showcases the use of SatCat5 IP-core wrappers and the SatCat5 embedded software libraries.
Target: Lattice iCE40-HX8K
This design acts as a passthrough converter, connecting the RJ45 port to a single SPI/UART port.
Target: Microsemi MPF-Splash + Xilinx XM105 breakout
This design hosts a SatCat5 Ethernet switch that connects the PolarFire's built-in RJ45 port to three Ethernet-over-SPI/UART ports on the breakout board.
Target: Digilent NetFPGA-1G-CML
This design contains a managed SatCat5 Ethernet switch that links the board's four RJ45 jacks and the two PMOD ports (as Ethernet-over-SPI/UART). It also contains a Microblaze processor and several ConfigBus peripherals.
Target: Custom prototype with a Xilinx Artix FPGA.
A larger example design with a SatCat5 Ethernet switch connecting one Ethernet PHY, four SGMII ports, and eight SPI/UART ports.
Target: Not applicable
This folder contains software examples for the Python API.
Target: Slingshot-1 cubesat
This folder contains interface control documents (ICDs) for the Slingshot modular interface. Slingshot uses SatCat5 to link together any number of smallsat payloads on a spacecraft LAN.
Target: Xilinx VC707 development board
This example is used to demonstrate operation of the VERDACT system, by synthesizing phase-locked 25 MHz in several asynchronous clock domains. It predates the higher-performance "zcu208_clksynth" design and is now obsolete.
Target: Xilinx VC707 development board
This design is similar to "arty_managed". It contains a SatCat5 Ethernet switch that connects the RJ45 port, the SFP port, and the USB-UART. It also contains a Microblaze processor and several ConfigBus peripherals.
Note that this design requires the "AVB" license for the Xilinx TEMAC IP-core, due to the use of PTP features.
Target: Xilinx VC707 development board
This design is similar to "vc707_managed", but eliminates the proprietary TEMAC IP-core. Use of VERDACT timestamps throughout the design allows superior time-transfer accuracy. It contains a SatCat5 Ethernet switch that connects the RJ45 port, the SFP port, the SMA connectors (used as an additional SGMII port), and the USB-UART. It also contains a Microblaze processor running an IP stack and a PTP client. GTX lanes attached to the FMC connector synthesize clocks for performance verification.
Additional documentation here.
Target: Xilinx ZCU208 development board
This example is used to demonstrate operation of the VERDACT system, by synthesizing a 125 MHz sine wave that is digitally phase-locked to an asynchronous reference. Use of sine waves instead of discrete-sampled square waves avoids discrete-time quantization error. This design was used to verify that VERDACT timestamps are colinear with sub-picosecond accuracy.
Target: ZedBoard Zynq-7000 Development Board
This design connects the Zynq PS Ethernet port to a PMOD Ethernet-over-SPI/UART port.
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This file is a part of SatCat5, licensed under CERN-OHL-W v2 or later.
You may redistribute and modify SatCat5 and make products using it under the weakly reciprocal variant of the CERN Open Hardware License, version 2 or (at your option) any later weakly reciprocal version.
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