Does not build with ghc-7.10.2

[tusj]

The package builds with ghc-7.8.4 but not with ghc-7.10.2.

The output error is:

[1 of 8] Compiling Language.Verilog.Parser.Tokens ( Language/Verilog/Parser/Tokens.hs, dist/build/Language/Verilog/Parser/Tokens.o )
[2 of 8] Compiling Language.Verilog.Parser.Preprocess ( Language/Verilog/Parser/Preprocess.hs, dist/build/Language/Verilog/Parser/Preprocess.o )
[3 of 8] Compiling Language.Verilog.Parser.Lex ( dist/build/Language/Verilog/Parser/Lex.hs, dist/build/Language/Verilog/Parser/Lex.o )

dist/build/Language/Verilog/Parser/Lex.hs:439:17:
    Pattern bindings containing unlifted types should use an outermost bang pattern:
      ((I# (ord_c))) = fromIntegral c
    In the expression:
      let
        (base) = alexIndexInt32OffAddr alex_base s
        ((I# (ord_c))) = fromIntegral c
        (offset) = (base +# ord_c)
        ....
      in
        case new_s of {
          -1# -> (new_acc, input)
          _ -> alex_scan_tkn
                 user
                 orig_input
                 (if c < 128 || c >= 192 then (len +# 1#) else len)
                 new_input
                 new_s
                 new_acc }
    In a case alternative:
        Just (c, new_input)
          -> let
               (base) = alexIndexInt32OffAddr alex_base s
               ((I# (ord_c))) = fromIntegral c
               ....
             in
               case new_s of {
                 -1# -> (new_acc, input)
                 _ -> alex_scan_tkn
                        user
                        orig_input
                        (if c < 128 || c >= 192 then (len +# 1#) else len)
                        new_input
                        new_s
                        new_acc }
    In the second argument of ‘seq’, namely
      ‘case alexGetByte input of {
         Nothing -> (new_acc, input)
         Just (c, new_input)
           -> let
                (base) = ...
                ....
              in
                case new_s of {
                  -1# -> ...
                  _ -> alex_scan_tkn
                         user
                         orig_input
                         (if c < 128 || c >= 192 then (len +# 1#) else len)
                         new_input
                         new_s
                         new_acc } }’

dist/build/Language/Verilog/Parser/Lex.hs:443:31:
    Couldn't match expected type ‘Bool’ with actual type ‘Int#’
    In the first argument of ‘(&&)’, namely ‘(offset >=# 0#)’
    In the expression: (offset >=# 0#) && (check ==# ord_c)
    In the expression:
      if (offset >=# 0#) && (check ==# ord_c) then
          alexIndexInt16OffAddr alex_table offset
      else
          alexIndexInt16OffAddr alex_deflt s

dist/build/Language/Verilog/Parser/Lex.hs:443:50:
    Couldn't match expected type ‘Bool’ with actual type ‘Int#’
    In the second argument of ‘(&&)’, namely ‘(check ==# ord_c)’
    In the expression: (offset >=# 0#) && (check ==# ord_c)
    In the expression:
      if (offset >=# 0#) && (check ==# ord_c) then
          alexIndexInt16OffAddr alex_table offset
      else
          alexIndexInt16OffAddr alex_deflt s