nor
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2 different variations of each cell was tested: NAND, INV, and NOR. Each cell was connected to a voltage source and a load capacitor. The experiment involved changing the input transition and the load cap. to measure the time delay. A python script was written to automate the process of writing a spice netlist for each cell to change the variables.
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Jun 17, 2023 - Python
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Nov 14, 2017 - HTML
Simple Implementation for Logic Gates Project represented in Physics (BS221) Course. Implemented with C++.
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Feb 17, 2021 - C++
Micron Flash interface with support x4 data width and supports AXI-Stream interface
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Jul 2, 2022 - VHDL
The trit package provides a Go implementation of three-level logic, including logical operations such as NOT, AND, OR, XOR, NAND, NOR, and XNOR.
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Jul 1, 2023 - Go
Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation
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Jun 4, 2023 - Python
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