Skip to content

Commit 3229830

Browse files
topperctopperc
committed
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx.
With Zfinx/Zdinx, f32/f64 are legal types for a GPR, we don't need a bitcast. This avoids turning fneg/fabs into bitwise operations purely because of these bitcasts. If the bitwise operations are faster for some reason on a Zfinx CPU, then that seems like it should be done for all fneg/fabs, not just ones near function arguments/returns. I don't have much interest in Zfinx, this just makes the code more similar to what I proposed for Zhinx in llvm#107446.
1 parent be1958f commit 3229830

File tree

11 files changed

+449
-505
lines changed

11 files changed

+449
-505
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19227,6 +19227,16 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
1922719227

1922819228
ArrayRef<MCPhysReg> ArgGPRs = RISCV::getArgGPRs(ABI);
1922919229

19230+
const RISCVSubtarget &STI =
19231+
State.getMachineFunction().getSubtarget<RISCVSubtarget>();
19232+
if ((ValVT == MVT::f32 && XLen == 32 && STI.hasStdExtZfinx()) ||
19233+
(ValVT == MVT::f64 && XLen == 64 && STI.hasStdExtZdinx())) {
19234+
if (MCRegister Reg = State.AllocateReg(ArgGPRs)) {
19235+
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
19236+
return false;
19237+
}
19238+
}
19239+
1923019240
if (UseGPRForF16_F32 && (ValVT == MVT::f16 || ValVT == MVT::bf16 ||
1923119241
(ValVT == MVT::f32 && XLen == 64))) {
1923219242
MCRegister Reg = State.AllocateReg(ArgGPRs);

‎llvm/test/CodeGen/RISCV/double-arith.ll‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -320,8 +320,7 @@ define double @fsgnjn_d(double %a, double %b) nounwind {
320320
;
321321
; RV64IZFINXZDINX-LABEL: fsgnjn_d:
322322
; RV64IZFINXZDINX: # %bb.0:
323-
; RV64IZFINXZDINX-NEXT: not a1, a1
324-
; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a0, a1
323+
; RV64IZFINXZDINX-NEXT: fsgnjn.d a0, a0, a1
325324
; RV64IZFINXZDINX-NEXT: ret
326325
;
327326
; RV32I-LABEL: fsgnjn_d:
@@ -852,9 +851,7 @@ define double @fnmadd_d_3(double %a, double %b, double %c) nounwind {
852851
; RV64IZFINXZDINX-LABEL: fnmadd_d_3:
853852
; RV64IZFINXZDINX: # %bb.0:
854853
; RV64IZFINXZDINX-NEXT: fmadd.d a0, a0, a1, a2
855-
; RV64IZFINXZDINX-NEXT: li a1, -1
856-
; RV64IZFINXZDINX-NEXT: slli a1, a1, 63
857-
; RV64IZFINXZDINX-NEXT: xor a0, a0, a1
854+
; RV64IZFINXZDINX-NEXT: fneg.d a0, a0
858855
; RV64IZFINXZDINX-NEXT: ret
859856
;
860857
; RV32I-LABEL: fnmadd_d_3:
@@ -900,10 +897,7 @@ define double @fnmadd_nsz(double %a, double %b, double %c) nounwind {
900897
;
901898
; RV64IZFINXZDINX-LABEL: fnmadd_nsz:
902899
; RV64IZFINXZDINX: # %bb.0:
903-
; RV64IZFINXZDINX-NEXT: fmadd.d a0, a0, a1, a2
904-
; RV64IZFINXZDINX-NEXT: li a1, -1
905-
; RV64IZFINXZDINX-NEXT: slli a1, a1, 63
906-
; RV64IZFINXZDINX-NEXT: xor a0, a0, a1
900+
; RV64IZFINXZDINX-NEXT: fnmadd.d a0, a0, a1, a2
907901
; RV64IZFINXZDINX-NEXT: ret
908902
;
909903
; RV32I-LABEL: fnmadd_nsz:

‎llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll‎

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -56,9 +56,7 @@ define double @fneg(double %a) nounwind {
5656
;
5757
; RV64IZFINXZDINX-LABEL: fneg:
5858
; RV64IZFINXZDINX: # %bb.0:
59-
; RV64IZFINXZDINX-NEXT: li a1, -1
60-
; RV64IZFINXZDINX-NEXT: slli a1, a1, 63
61-
; RV64IZFINXZDINX-NEXT: xor a0, a0, a1
59+
; RV64IZFINXZDINX-NEXT: fneg.d a0, a0
6260
; RV64IZFINXZDINX-NEXT: ret
6361
%1 = fneg double %a
6462
ret double %1
@@ -99,8 +97,7 @@ define double @fabs(double %a) nounwind {
9997
;
10098
; RV64IZFINXZDINX-LABEL: fabs:
10199
; RV64IZFINXZDINX: # %bb.0:
102-
; RV64IZFINXZDINX-NEXT: slli a0, a0, 1
103-
; RV64IZFINXZDINX-NEXT: srli a0, a0, 1
100+
; RV64IZFINXZDINX-NEXT: fabs.d a0, a0
104101
; RV64IZFINXZDINX-NEXT: ret
105102
%1 = call double @llvm.fabs.f64(double %a)
106103
ret double %1
@@ -165,8 +162,7 @@ define double @fcopysign_fneg(double %a, double %b) nounwind {
165162
;
166163
; RV64IZFINXZDINX-LABEL: fcopysign_fneg:
167164
; RV64IZFINXZDINX: # %bb.0:
168-
; RV64IZFINXZDINX-NEXT: not a1, a1
169-
; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a0, a1
165+
; RV64IZFINXZDINX-NEXT: fsgnjn.d a0, a0, a1
170166
; RV64IZFINXZDINX-NEXT: ret
171167
%1 = fneg double %b
172168
%2 = call double @llvm.copysign.f64(double %a, double %1)

‎llvm/test/CodeGen/RISCV/double-imm.ll‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -115,8 +115,7 @@ define double @double_negative_zero(ptr %pd) nounwind {
115115
;
116116
; CHECKRV64ZDINX-LABEL: double_negative_zero:
117117
; CHECKRV64ZDINX: # %bb.0:
118-
; CHECKRV64ZDINX-NEXT: li a0, -1
119-
; CHECKRV64ZDINX-NEXT: slli a0, a0, 63
118+
; CHECKRV64ZDINX-NEXT: fneg.d a0, zero
120119
; CHECKRV64ZDINX-NEXT: ret
121120
ret double -0.0
122121
}
@@ -160,12 +159,11 @@ define dso_local double @negzero_sel(i16 noundef %a, double noundef %d) nounwind
160159
; CHECKRV64ZDINX-LABEL: negzero_sel:
161160
; CHECKRV64ZDINX: # %bb.0: # %entry
162161
; CHECKRV64ZDINX-NEXT: slli a2, a0, 48
162+
; CHECKRV64ZDINX-NEXT: mv a0, a1
163163
; CHECKRV64ZDINX-NEXT: beqz a2, .LBB4_2
164164
; CHECKRV64ZDINX-NEXT: # %bb.1: # %entry
165165
; CHECKRV64ZDINX-NEXT: fneg.d a0, zero
166-
; CHECKRV64ZDINX-NEXT: ret
167-
; CHECKRV64ZDINX-NEXT: .LBB4_2:
168-
; CHECKRV64ZDINX-NEXT: mv a0, a1
166+
; CHECKRV64ZDINX-NEXT: .LBB4_2: # %entry
169167
; CHECKRV64ZDINX-NEXT: ret
170168
entry:
171169
%tobool.not = icmp eq i16 %a, 0

‎llvm/test/CodeGen/RISCV/double-intrinsics.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -684,8 +684,7 @@ define double @fabs_f64(double %a) nounwind {
684684
;
685685
; RV64IZFINXZDINX-LABEL: fabs_f64:
686686
; RV64IZFINXZDINX: # %bb.0:
687-
; RV64IZFINXZDINX-NEXT: slli a0, a0, 1
688-
; RV64IZFINXZDINX-NEXT: srli a0, a0, 1
687+
; RV64IZFINXZDINX-NEXT: fabs.d a0, a0
689688
; RV64IZFINXZDINX-NEXT: ret
690689
;
691690
; RV32I-LABEL: fabs_f64:

‎llvm/test/CodeGen/RISCV/float-arith.ll‎

Lines changed: 25 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,9 @@
44
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
55
; RUN: -target-abi=lp64f | FileCheck -check-prefix=CHECKIF %s
66
; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
7-
; RUN: -target-abi=ilp32 | FileCheck -check-prefix=CHECKIZFINX %s
7+
; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZFINX,RV32IZFINX %s
88
; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
9-
; RUN: -target-abi=lp64 | FileCheck -check-prefix=CHECKIZFINX %s
9+
; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZFINX,RV64IZFINX %s
1010
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
1111
; RUN: | FileCheck -check-prefix=RV32I %s
1212
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
@@ -706,12 +706,18 @@ define float @fnmadd_s_3(float %a, float %b, float %c) nounwind {
706706
; CHECKIF-NEXT: fneg.s fa0, fa5
707707
; CHECKIF-NEXT: ret
708708
;
709-
; CHECKIZFINX-LABEL: fnmadd_s_3:
710-
; CHECKIZFINX: # %bb.0:
711-
; CHECKIZFINX-NEXT: fmadd.s a0, a0, a1, a2
712-
; CHECKIZFINX-NEXT: lui a1, 524288
713-
; CHECKIZFINX-NEXT: xor a0, a0, a1
714-
; CHECKIZFINX-NEXT: ret
709+
; RV32IZFINX-LABEL: fnmadd_s_3:
710+
; RV32IZFINX: # %bb.0:
711+
; RV32IZFINX-NEXT: fmadd.s a0, a0, a1, a2
712+
; RV32IZFINX-NEXT: fneg.s a0, a0
713+
; RV32IZFINX-NEXT: ret
714+
;
715+
; RV64IZFINX-LABEL: fnmadd_s_3:
716+
; RV64IZFINX: # %bb.0:
717+
; RV64IZFINX-NEXT: fmadd.s a0, a0, a1, a2
718+
; RV64IZFINX-NEXT: lui a1, 524288
719+
; RV64IZFINX-NEXT: xor a0, a0, a1
720+
; RV64IZFINX-NEXT: ret
715721
;
716722
; RV32I-LABEL: fnmadd_s_3:
717723
; RV32I: # %bb.0:
@@ -755,12 +761,17 @@ define float @fnmadd_nsz(float %a, float %b, float %c) nounwind {
755761
; CHECKIF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
756762
; CHECKIF-NEXT: ret
757763
;
758-
; CHECKIZFINX-LABEL: fnmadd_nsz:
759-
; CHECKIZFINX: # %bb.0:
760-
; CHECKIZFINX-NEXT: fmadd.s a0, a0, a1, a2
761-
; CHECKIZFINX-NEXT: lui a1, 524288
762-
; CHECKIZFINX-NEXT: xor a0, a0, a1
763-
; CHECKIZFINX-NEXT: ret
764+
; RV32IZFINX-LABEL: fnmadd_nsz:
765+
; RV32IZFINX: # %bb.0:
766+
; RV32IZFINX-NEXT: fnmadd.s a0, a0, a1, a2
767+
; RV32IZFINX-NEXT: ret
768+
;
769+
; RV64IZFINX-LABEL: fnmadd_nsz:
770+
; RV64IZFINX: # %bb.0:
771+
; RV64IZFINX-NEXT: fmadd.s a0, a0, a1, a2
772+
; RV64IZFINX-NEXT: lui a1, 524288
773+
; RV64IZFINX-NEXT: xor a0, a0, a1
774+
; RV64IZFINX-NEXT: ret
764775
;
765776
; RV32I-LABEL: fnmadd_nsz:
766777
; RV32I: # %bb.0:

‎llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -33,8 +33,7 @@ define float @fneg(float %a) nounwind {
3333
;
3434
; RV32IZFINX-LABEL: fneg:
3535
; RV32IZFINX: # %bb.0:
36-
; RV32IZFINX-NEXT: lui a1, 524288
37-
; RV32IZFINX-NEXT: xor a0, a0, a1
36+
; RV32IZFINX-NEXT: fneg.s a0, a0
3837
; RV32IZFINX-NEXT: ret
3938
;
4039
; RV64I-LABEL: fneg:
@@ -75,8 +74,7 @@ define float @fabs(float %a) nounwind {
7574
;
7675
; RV32IZFINX-LABEL: fabs:
7776
; RV32IZFINX: # %bb.0:
78-
; RV32IZFINX-NEXT: slli a0, a0, 1
79-
; RV32IZFINX-NEXT: srli a0, a0, 1
77+
; RV32IZFINX-NEXT: fabs.s a0, a0
8078
; RV32IZFINX-NEXT: ret
8179
;
8280
; RV64I-LABEL: fabs:
@@ -128,8 +126,7 @@ define float @fcopysign_fneg(float %a, float %b) nounwind {
128126
;
129127
; RV32IZFINX-LABEL: fcopysign_fneg:
130128
; RV32IZFINX: # %bb.0:
131-
; RV32IZFINX-NEXT: not a1, a1
132-
; RV32IZFINX-NEXT: fsgnj.s a0, a0, a1
129+
; RV32IZFINX-NEXT: fsgnjn.s a0, a0, a1
133130
; RV32IZFINX-NEXT: ret
134131
;
135132
; RV64I-LABEL: fcopysign_fneg:

‎llvm/test/CodeGen/RISCV/float-intrinsics.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -688,8 +688,7 @@ define float @fabs_f32(float %a) nounwind {
688688
;
689689
; RV32IZFINX-LABEL: fabs_f32:
690690
; RV32IZFINX: # %bb.0:
691-
; RV32IZFINX-NEXT: slli a0, a0, 1
692-
; RV32IZFINX-NEXT: srli a0, a0, 1
691+
; RV32IZFINX-NEXT: fabs.s a0, a0
693692
; RV32IZFINX-NEXT: ret
694693
;
695694
; RV64IF-LABEL: fabs_f32:

0 commit comments

Comments
 (0)