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ftgmac100.c
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Faraday FTGMAC100 Gigabit Ethernet
*
* (C) Copyright 2009-2011 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/crc32.h>
#include <linux/if_vlan.h>
#include <linux/of_net.h>
#include <linux/phy_fixed.h>
#include <net/ip.h>
#include <net/ncsi.h>
#include "ftgmac100.h"
#define DRV_NAME "ftgmac100"
/* Arbitrary values, I am not sure the HW has limits */
#define MAX_RX_QUEUE_ENTRIES 1024
#define MAX_TX_QUEUE_ENTRIES 1024
#define MIN_RX_QUEUE_ENTRIES 32
#define MIN_TX_QUEUE_ENTRIES 32
/* Defaults */
#define DEF_RX_QUEUE_ENTRIES 128
#define DEF_TX_QUEUE_ENTRIES 128
#define MAX_PKT_SIZE 1536
#define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
/* Min number of tx ring entries before stopping queue */
#define TX_THRESHOLD (MAX_SKB_FRAGS + 1)
#define FTGMAC_100MHZ 100000000
#define FTGMAC_25MHZ 25000000
/* For NC-SI to register a fixed-link phy device */
static struct fixed_phy_status ncsi_phy_status = {
.link = 1,
.speed = SPEED_100,
.duplex = DUPLEX_FULL,
.pause = 0,
.asym_pause = 0
};
struct ftgmac100 {
/* Registers */
struct resource *res;
void __iomem *base;
/* Rx ring */
unsigned int rx_q_entries;
struct ftgmac100_rxdes *rxdes;
dma_addr_t rxdes_dma;
struct sk_buff **rx_skbs;
unsigned int rx_pointer;
u32 rxdes0_edorr_mask;
/* Tx ring */
unsigned int tx_q_entries;
struct ftgmac100_txdes *txdes;
dma_addr_t txdes_dma;
struct sk_buff **tx_skbs;
unsigned int tx_clean_pointer;
unsigned int tx_pointer;
u32 txdes0_edotr_mask;
/* Used to signal the reset task of ring change request */
unsigned int new_rx_q_entries;
unsigned int new_tx_q_entries;
/* Scratch page to use when rx skb alloc fails */
void *rx_scratch;
dma_addr_t rx_scratch_dma;
/* Component structures */
struct net_device *netdev;
struct device *dev;
struct ncsi_dev *ndev;
struct napi_struct napi;
struct work_struct reset_task;
struct mii_bus *mii_bus;
struct clk *clk;
/* AST2500/AST2600 RMII ref clock gate */
struct clk *rclk;
/* Link management */
int cur_speed;
int cur_duplex;
bool use_ncsi;
/* Multicast filter settings */
u32 maht0;
u32 maht1;
/* Flow control settings */
bool tx_pause;
bool rx_pause;
bool aneg_pause;
/* Misc */
bool need_mac_restart;
bool is_aspeed;
};
static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
{
struct net_device *netdev = priv->netdev;
int i;
/* NOTE: reset clears all registers */
iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
priv->base + FTGMAC100_OFFSET_MACCR);
for (i = 0; i < 200; i++) {
unsigned int maccr;
maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
if (!(maccr & FTGMAC100_MACCR_SW_RST))
return 0;
udelay(1);
}
netdev_err(netdev, "Hardware reset failed\n");
return -EIO;
}
static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
{
u32 maccr = 0;
switch (priv->cur_speed) {
case SPEED_10:
case 0: /* no link */
break;
case SPEED_100:
maccr |= FTGMAC100_MACCR_FAST_MODE;
break;
case SPEED_1000:
maccr |= FTGMAC100_MACCR_GIGA_MODE;
break;
default:
netdev_err(priv->netdev, "Unknown speed %d !\n",
priv->cur_speed);
break;
}
/* (Re)initialize the queue pointers */
priv->rx_pointer = 0;
priv->tx_clean_pointer = 0;
priv->tx_pointer = 0;
/* The doc says reset twice with 10us interval */
if (ftgmac100_reset_mac(priv, maccr))
return -EIO;
usleep_range(10, 1000);
return ftgmac100_reset_mac(priv, maccr);
}
static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac)
{
unsigned int maddr = mac[0] << 8 | mac[1];
unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
}
static int ftgmac100_initial_mac(struct ftgmac100 *priv)
{
u8 mac[ETH_ALEN];
unsigned int m;
unsigned int l;
int err;
err = of_get_ethdev_address(priv->dev->of_node, priv->netdev);
if (err == -EPROBE_DEFER)
return err;
if (!err) {
dev_info(priv->dev, "Read MAC address %pM from device tree\n",
priv->netdev->dev_addr);
return 0;
}
m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
mac[0] = (m >> 8) & 0xff;
mac[1] = m & 0xff;
mac[2] = (l >> 24) & 0xff;
mac[3] = (l >> 16) & 0xff;
mac[4] = (l >> 8) & 0xff;
mac[5] = l & 0xff;
if (is_valid_ether_addr(mac)) {
eth_hw_addr_set(priv->netdev, mac);
dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
} else {
eth_hw_addr_random(priv->netdev);
dev_info(priv->dev, "Generated random MAC address %pM\n",
priv->netdev->dev_addr);
}
return 0;
}
static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
{
int ret;
ret = eth_prepare_mac_addr_change(dev, p);
if (ret < 0)
return ret;
eth_commit_mac_addr_change(dev, p);
ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr);
return 0;
}
static void ftgmac100_config_pause(struct ftgmac100 *priv)
{
u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16);
/* Throttle tx queue when receiving pause frames */
if (priv->rx_pause)
fcr |= FTGMAC100_FCR_FC_EN;
/* Enables sending pause frames when the RX queue is past a
* certain threshold.
*/
if (priv->tx_pause)
fcr |= FTGMAC100_FCR_FCTHR_EN;
iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR);
}
static void ftgmac100_init_hw(struct ftgmac100 *priv)
{
u32 reg, rfifo_sz, tfifo_sz;
/* Clear stale interrupts */
reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR);
/* Setup RX ring buffer base */
iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR);
/* Setup TX ring buffer base */
iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
/* Configure RX buffer size */
iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE),
priv->base + FTGMAC100_OFFSET_RBSR);
/* Set RX descriptor autopoll */
iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
priv->base + FTGMAC100_OFFSET_APTC);
/* Write MAC address */
ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr);
/* Write multicast filter */
iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
/* Configure descriptor sizes and increase burst sizes according
* to values in Aspeed SDK. The FIFO arbitration is enabled and
* the thresholds set based on the recommended values in the
* AST2400 specification.
*/
iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */
FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */
FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */
FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */
FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */
priv->base + FTGMAC100_OFFSET_DBLAC);
/* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
* mitigation doesn't seem to provide any benefit with NAPI so leave
* it at that.
*/
iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
FTGMAC100_ITC_TXINT_THR(1),
priv->base + FTGMAC100_OFFSET_ITC);
/* Configure FIFO sizes in the TPAFCR register */
reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR);
rfifo_sz = reg & 0x00000007;
tfifo_sz = (reg >> 3) & 0x00000007;
reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR);
reg &= ~0x3f000000;
reg |= (tfifo_sz << 27);
reg |= (rfifo_sz << 24);
iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR);
}
static void ftgmac100_start_hw(struct ftgmac100 *priv)
{
u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
/* Keep the original GMAC and FAST bits */
maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
/* Add all the main enable bits */
maccr |= FTGMAC100_MACCR_TXDMA_EN |
FTGMAC100_MACCR_RXDMA_EN |
FTGMAC100_MACCR_TXMAC_EN |
FTGMAC100_MACCR_RXMAC_EN |
FTGMAC100_MACCR_CRC_APD |
FTGMAC100_MACCR_PHY_LINK_LEVEL |
FTGMAC100_MACCR_RX_RUNT |
FTGMAC100_MACCR_RX_BROADPKT;
/* Add other bits as needed */
if (priv->cur_duplex == DUPLEX_FULL)
maccr |= FTGMAC100_MACCR_FULLDUP;
if (priv->netdev->flags & IFF_PROMISC)
maccr |= FTGMAC100_MACCR_RX_ALL;
if (priv->netdev->flags & IFF_ALLMULTI)
maccr |= FTGMAC100_MACCR_RX_MULTIPKT;
else if (netdev_mc_count(priv->netdev))
maccr |= FTGMAC100_MACCR_HT_MULTI_EN;
/* Vlan filtering enabled */
if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
maccr |= FTGMAC100_MACCR_RM_VLAN;
/* Hit the HW */
iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
}
static void ftgmac100_stop_hw(struct ftgmac100 *priv)
{
iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
}
static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv)
{
struct netdev_hw_addr *ha;
priv->maht1 = 0;
priv->maht0 = 0;
netdev_for_each_mc_addr(ha, priv->netdev) {
u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr);
crc_val = (~(crc_val >> 2)) & 0x3f;
if (crc_val >= 32)
priv->maht1 |= 1ul << (crc_val - 32);
else
priv->maht0 |= 1ul << (crc_val);
}
}
static void ftgmac100_set_rx_mode(struct net_device *netdev)
{
struct ftgmac100 *priv = netdev_priv(netdev);
/* Setup the hash filter */
ftgmac100_calc_mc_hash(priv);
/* Interface down ? that's all there is to do */
if (!netif_running(netdev))
return;
/* Update the HW */
iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
/* Reconfigure MACCR */
ftgmac100_start_hw(priv);
}
static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
struct ftgmac100_rxdes *rxdes, gfp_t gfp)
{
struct net_device *netdev = priv->netdev;
struct sk_buff *skb;
dma_addr_t map;
int err = 0;
skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
if (unlikely(!skb)) {
if (net_ratelimit())
netdev_warn(netdev, "failed to allocate rx skb\n");
err = -ENOMEM;
map = priv->rx_scratch_dma;
} else {
map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
DMA_FROM_DEVICE);
if (unlikely(dma_mapping_error(priv->dev, map))) {
if (net_ratelimit())
netdev_err(netdev, "failed to map rx page\n");
dev_kfree_skb_any(skb);
map = priv->rx_scratch_dma;
skb = NULL;
err = -ENOMEM;
}
}
/* Store skb */
priv->rx_skbs[entry] = skb;
/* Store DMA address into RX desc */
rxdes->rxdes3 = cpu_to_le32(map);
/* Ensure the above is ordered vs clearing the OWN bit */
dma_wmb();
/* Clean status (which resets own bit) */
if (entry == (priv->rx_q_entries - 1))
rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
else
rxdes->rxdes0 = 0;
return err;
}
static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
unsigned int pointer)
{
return (pointer + 1) & (priv->rx_q_entries - 1);
}
static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
{
struct net_device *netdev = priv->netdev;
if (status & FTGMAC100_RXDES0_RX_ERR)
netdev->stats.rx_errors++;
if (status & FTGMAC100_RXDES0_CRC_ERR)
netdev->stats.rx_crc_errors++;
if (status & (FTGMAC100_RXDES0_FTL |
FTGMAC100_RXDES0_RUNT |
FTGMAC100_RXDES0_RX_ODD_NB))
netdev->stats.rx_length_errors++;
}
static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
{
struct net_device *netdev = priv->netdev;
struct ftgmac100_rxdes *rxdes;
struct sk_buff *skb;
unsigned int pointer, size;
u32 status, csum_vlan;
dma_addr_t map;
/* Grab next RX descriptor */
pointer = priv->rx_pointer;
rxdes = &priv->rxdes[pointer];
/* Grab descriptor status */
status = le32_to_cpu(rxdes->rxdes0);
/* Do we have a packet ? */
if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
return false;
/* Order subsequent reads with the test for the ready bit */
dma_rmb();
/* We don't cope with fragmented RX packets */
if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
!(status & FTGMAC100_RXDES0_LRS)))
goto drop;
/* Grab received size and csum vlan field in the descriptor */
size = status & FTGMAC100_RXDES0_VDBC;
csum_vlan = le32_to_cpu(rxdes->rxdes1);
/* Any error (other than csum offload) flagged ? */
if (unlikely(status & RXDES0_ANY_ERROR)) {
/* Correct for incorrect flagging of runt packets
* with vlan tags... Just accept a runt packet that
* has been flagged as vlan and whose size is at
* least 60 bytes.
*/
if ((status & FTGMAC100_RXDES0_RUNT) &&
(csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
(size >= 60))
status &= ~FTGMAC100_RXDES0_RUNT;
/* Any error still in there ? */
if (status & RXDES0_ANY_ERROR) {
ftgmac100_rx_packet_error(priv, status);
goto drop;
}
}
/* If the packet had no skb (failed to allocate earlier)
* then try to allocate one and skip
*/
skb = priv->rx_skbs[pointer];
if (!unlikely(skb)) {
ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
goto drop;
}
if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
netdev->stats.multicast++;
/* If the HW found checksum errors, bounce it to software.
*
* If we didn't, we need to see if the packet was recognized
* by HW as one of the supported checksummed protocols before
* we accept the HW test results.
*/
if (netdev->features & NETIF_F_RXCSUM) {
u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
FTGMAC100_RXDES1_IP_CHKSUM_ERR;
if ((csum_vlan & err_bits) ||
!(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
skb->ip_summed = CHECKSUM_NONE;
else
skb->ip_summed = CHECKSUM_UNNECESSARY;
}
/* Transfer received size to skb */
skb_put(skb, size);
/* Extract vlan tag */
if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
(csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL))
__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
csum_vlan & 0xffff);
/* Tear down DMA mapping, do necessary cache management */
map = le32_to_cpu(rxdes->rxdes3);
#if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
/* When we don't have an iommu, we can save cycles by not
* invalidating the cache for the part of the packet that
* wasn't received.
*/
dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
#else
dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
#endif
/* Resplenish rx ring */
ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
skb->protocol = eth_type_trans(skb, netdev);
netdev->stats.rx_packets++;
netdev->stats.rx_bytes += size;
/* push packet to protocol stack */
if (skb->ip_summed == CHECKSUM_NONE)
netif_receive_skb(skb);
else
napi_gro_receive(&priv->napi, skb);
(*processed)++;
return true;
drop:
/* Clean rxdes0 (which resets own bit) */
rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
netdev->stats.rx_dropped++;
return true;
}
static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
unsigned int index)
{
if (index == (priv->tx_q_entries - 1))
return priv->txdes0_edotr_mask;
else
return 0;
}
static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv,
unsigned int pointer)
{
return (pointer + 1) & (priv->tx_q_entries - 1);
}
static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
{
/* Returns the number of available slots in the TX queue
*
* This always leaves one free slot so we don't have to
* worry about empty vs. full, and this simplifies the
* test for ftgmac100_tx_buf_cleanable() below
*/
return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
(priv->tx_q_entries - 1);
}
static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
{
return priv->tx_pointer != priv->tx_clean_pointer;
}
static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
unsigned int pointer,
struct sk_buff *skb,
struct ftgmac100_txdes *txdes,
u32 ctl_stat)
{
dma_addr_t map = le32_to_cpu(txdes->txdes3);
size_t len;
if (ctl_stat & FTGMAC100_TXDES0_FTS) {
len = skb_headlen(skb);
dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
} else {
len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
}
/* Free SKB on last segment */
if (ctl_stat & FTGMAC100_TXDES0_LTS)
dev_kfree_skb(skb);
priv->tx_skbs[pointer] = NULL;
}
static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
{
struct net_device *netdev = priv->netdev;
struct ftgmac100_txdes *txdes;
struct sk_buff *skb;
unsigned int pointer;
u32 ctl_stat;
pointer = priv->tx_clean_pointer;
txdes = &priv->txdes[pointer];
ctl_stat = le32_to_cpu(txdes->txdes0);
if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
return false;
skb = priv->tx_skbs[pointer];
netdev->stats.tx_packets++;
netdev->stats.tx_bytes += skb->len;
ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
/* Ensure the descriptor config is visible before setting the tx
* pointer.
*/
smp_wmb();
priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer);
return true;
}
static void ftgmac100_tx_complete(struct ftgmac100 *priv)
{
struct net_device *netdev = priv->netdev;
/* Process all completed packets */
while (ftgmac100_tx_buf_cleanable(priv) &&
ftgmac100_tx_complete_packet(priv))
;
/* Restart queue if needed */
smp_mb();
if (unlikely(netif_queue_stopped(netdev) &&
ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
struct netdev_queue *txq;
txq = netdev_get_tx_queue(netdev, 0);
__netif_tx_lock(txq, smp_processor_id());
if (netif_queue_stopped(netdev) &&
ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
netif_wake_queue(netdev);
__netif_tx_unlock(txq);
}
}
static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
{
if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
u8 ip_proto = ip_hdr(skb)->protocol;
*csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
switch(ip_proto) {
case IPPROTO_TCP:
*csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
return true;
case IPPROTO_UDP:
*csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
return true;
case IPPROTO_IP:
return true;
}
}
return skb_checksum_help(skb) == 0;
}
static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb,
struct net_device *netdev)
{
struct ftgmac100 *priv = netdev_priv(netdev);
struct ftgmac100_txdes *txdes, *first;
unsigned int pointer, nfrags, len, i, j;
u32 f_ctl_stat, ctl_stat, csum_vlan;
dma_addr_t map;
/* The HW doesn't pad small frames */
if (eth_skb_pad(skb)) {
netdev->stats.tx_dropped++;
return NETDEV_TX_OK;
}
/* Reject oversize packets */
if (unlikely(skb->len > MAX_PKT_SIZE)) {
if (net_ratelimit())
netdev_dbg(netdev, "tx packet too big\n");
goto drop;
}
/* Do we have a limit on #fragments ? I yet have to get a reply
* from Aspeed. If there's one I haven't hit it.
*/
nfrags = skb_shinfo(skb)->nr_frags;
/* Setup HW checksumming */
csum_vlan = 0;
if (skb->ip_summed == CHECKSUM_PARTIAL &&
!ftgmac100_prep_tx_csum(skb, &csum_vlan))
goto drop;
/* Add VLAN tag */
if (skb_vlan_tag_present(skb)) {
csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG;
csum_vlan |= skb_vlan_tag_get(skb) & 0xffff;
}
/* Get header len */
len = skb_headlen(skb);
/* Map the packet head */
map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
if (dma_mapping_error(priv->dev, map)) {
if (net_ratelimit())
netdev_err(netdev, "map tx packet head failed\n");
goto drop;
}
/* Grab the next free tx descriptor */
pointer = priv->tx_pointer;
txdes = first = &priv->txdes[pointer];
/* Setup it up with the packet head. Don't write the head to the
* ring just yet
*/
priv->tx_skbs[pointer] = skb;
f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
f_ctl_stat |= FTGMAC100_TXDES0_FTS;
if (nfrags == 0)
f_ctl_stat |= FTGMAC100_TXDES0_LTS;
txdes->txdes3 = cpu_to_le32(map);
txdes->txdes1 = cpu_to_le32(csum_vlan);
/* Next descriptor */
pointer = ftgmac100_next_tx_pointer(priv, pointer);
/* Add the fragments */
for (i = 0; i < nfrags; i++) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
len = skb_frag_size(frag);
/* Map it */
map = skb_frag_dma_map(priv->dev, frag, 0, len,
DMA_TO_DEVICE);
if (dma_mapping_error(priv->dev, map))
goto dma_err;
/* Setup descriptor */
priv->tx_skbs[pointer] = skb;
txdes = &priv->txdes[pointer];
ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
if (i == (nfrags - 1))
ctl_stat |= FTGMAC100_TXDES0_LTS;
txdes->txdes0 = cpu_to_le32(ctl_stat);
txdes->txdes1 = 0;
txdes->txdes3 = cpu_to_le32(map);
/* Next one */
pointer = ftgmac100_next_tx_pointer(priv, pointer);
}
/* Order the previous packet and descriptor udpates
* before setting the OWN bit on the first descriptor.
*/
dma_wmb();
first->txdes0 = cpu_to_le32(f_ctl_stat);
/* Ensure the descriptor config is visible before setting the tx
* pointer.
*/
smp_wmb();
/* Update next TX pointer */
priv->tx_pointer = pointer;
/* If there isn't enough room for all the fragments of a new packet
* in the TX ring, stop the queue. The sequence below is race free
* vs. a concurrent restart in ftgmac100_poll()
*/
if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
netif_stop_queue(netdev);
/* Order the queue stop with the test below */
smp_mb();
if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
netif_wake_queue(netdev);
}
/* Poke transmitter to read the updated TX descriptors */
iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
return NETDEV_TX_OK;
dma_err:
if (net_ratelimit())
netdev_err(netdev, "map tx fragment failed\n");
/* Free head */
pointer = priv->tx_pointer;
ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
/* Then all fragments */
for (j = 0; j < i; j++) {
pointer = ftgmac100_next_tx_pointer(priv, pointer);
txdes = &priv->txdes[pointer];
ctl_stat = le32_to_cpu(txdes->txdes0);
ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
}
/* This cannot be reached if we successfully mapped the
* last fragment, so we know ftgmac100_free_tx_packet()
* hasn't freed the skb yet.
*/
drop:
/* Drop the packet */
dev_kfree_skb_any(skb);
netdev->stats.tx_dropped++;
return NETDEV_TX_OK;
}
static void ftgmac100_free_buffers(struct ftgmac100 *priv)
{
int i;
/* Free all RX buffers */
for (i = 0; i < priv->rx_q_entries; i++) {
struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
struct sk_buff *skb = priv->rx_skbs[i];
dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
if (!skb)
continue;
priv->rx_skbs[i] = NULL;
dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
dev_kfree_skb_any(skb);
}
/* Free all TX buffers */
for (i = 0; i < priv->tx_q_entries; i++) {
struct ftgmac100_txdes *txdes = &priv->txdes[i];
struct sk_buff *skb = priv->tx_skbs[i];
if (!skb)
continue;
ftgmac100_free_tx_packet(priv, i, skb, txdes,
le32_to_cpu(txdes->txdes0));
}
}
static void ftgmac100_free_rings(struct ftgmac100 *priv)
{
/* Free skb arrays */
kfree(priv->rx_skbs);
kfree(priv->tx_skbs);
/* Free descriptors */
if (priv->rxdes)
dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES *
sizeof(struct ftgmac100_rxdes),
priv->rxdes, priv->rxdes_dma);
priv->rxdes = NULL;
if (priv->txdes)
dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES *
sizeof(struct ftgmac100_txdes),
priv->txdes, priv->txdes_dma);
priv->txdes = NULL;
/* Free scratch packet buffer */
if (priv->rx_scratch)
dma_free_coherent(priv->dev, RX_BUF_SIZE,
priv->rx_scratch, priv->rx_scratch_dma);
}
static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
{
/* Allocate skb arrays */
priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *),
GFP_KERNEL);
if (!priv->rx_skbs)
return -ENOMEM;
priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *),
GFP_KERNEL);
if (!priv->tx_skbs)
return -ENOMEM;
/* Allocate descriptors */
priv->rxdes = dma_alloc_coherent(priv->dev,
MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes),
&priv->rxdes_dma, GFP_KERNEL);
if (!priv->rxdes)
return -ENOMEM;
priv->txdes = dma_alloc_coherent(priv->dev,
MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes),
&priv->txdes_dma, GFP_KERNEL);
if (!priv->txdes)
return -ENOMEM;
/* Allocate scratch packet buffer */
priv->rx_scratch = dma_alloc_coherent(priv->dev,
RX_BUF_SIZE,
&priv->rx_scratch_dma,
GFP_KERNEL);
if (!priv->rx_scratch)
return -ENOMEM;
return 0;
}
static void ftgmac100_init_rings(struct ftgmac100 *priv)
{
struct ftgmac100_rxdes *rxdes = NULL;
struct ftgmac100_txdes *txdes = NULL;
int i;
/* Update entries counts */
priv->rx_q_entries = priv->new_rx_q_entries;
priv->tx_q_entries = priv->new_tx_q_entries;
if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES))
return;
/* Initialize RX ring */
for (i = 0; i < priv->rx_q_entries; i++) {
rxdes = &priv->rxdes[i];
rxdes->rxdes0 = 0;
rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
}
/* Mark the end of the ring */
rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES))
return;
/* Initialize TX ring */
for (i = 0; i < priv->tx_q_entries; i++) {
txdes = &priv->txdes[i];
txdes->txdes0 = 0;