Potential bus collisions in efinix spi flash access?

[harbaum]

On efinix the spi flash is accessed directly from the ftx232 bypassing the FPGA completely. It's not obvious to me how bus collisions are prevented. The openFPGAloader triggers CRESET before accessing flash. This should imho cause the FPGA to reconfigure itself and thus to try a spi flash boot. This would potentially collide with the ft2232 also accessing the flash. But obviously that doesn't happen neither with a real ft2232 nor with my pico. But why? Edit: This is prevented by keeping the FPGA in reset during SPI access.

A similar issue arises once the flash has been accessed by openFPGAloader. After spi flash access the openFPGAloader triggers creset and waits for cdone. This also works with a ft2232. But it does not work with my pico as a replecement. After accessing the spi flash openfpgaloader is still in MPSSE mode with SCK, DI and /CS being driven. In my setup this prevents the FPGA from rebooting. So there is a collision. Why isn't there one with a real ft2232? Or is there one and the ft2232 simply has the lower drive strength and the FPGA just wins this battle?

I asked the same question to the efinix support at https://forum.efinix.net/t/ft2232-to-release-spi-after-flashing/2738

[harbaum]

These lines actually suggest that the SPI is being released:

openFPGALoader/src/efinix.cpp

Lines 278 to 279 in 5644850

	/* release SPI access. XXX later: refactor to use reset() and make sure the behavior is the same */
	_spi->gpio_set(_rst_pin | _oe_pin);

But is it really? How?

[harbaum]

I tried adding

  	// stop driving the spi bus
	_spi->gpio_set_input(0x0f);

right before resetting the FPGA and waiting for cdone and that does the trick for me. Is there a "correct" way to release the SPI?