Fails to parse correct code

[numero-744]

Hi there 👋

I have tried to use mergiraf on https://github.com/openhwgroup/cva6/blob/master/core/scoreboard.sv and it fails to parse this file using tree-sitter-verilog.
The scoreboard.sv file is correctly parsed by verilator, questa and vcs, but not by tree-sitter-verilog 🤔
Well, CVA6 looks like an interesting playground for integration testing 😉

There seem to be different errors that I have not yet identified.
(Maybe system tasks (eg: $clog2) and for loops?)

I have reproduced the issue running tree-sitter-cli directly.

% tree-sitter parse --scope source.verilog core/scoreboard.sv
...
core/scoreboard.sv	Parse:    3.94 ms	 3893 bytes/ms	(ERROR [121, 4] - [121, 61])

Is there anybody motivated to fix this?
Else I can have a look this week-end.

I have the following document:

SystemVerilog 3.1a
Language Reference Manual
Accellera’s Extensions to Verilog®

It seems the standard you have implemented is not the one I have.
The sections have changed so I cannot map between grammar.js and the specification.

PS: Wondering if tree-sitter performs pre-processing for `include and macros.
Otherwise, are there workarounds to avoid false errors on ugly but correct code?