memory_synth.v

/* Generated by Yosys 0.29+44 (git sha1 88c849d11, clang 6.0.0-1ubuntu2 -fPIC -Os) */

(* dynports =  1  *)
(* top =  1  *)
(* src = "memory.v:1.1-14.10" *)
module memory(CLK, ADDR, DIN, DOUT);
  wire _0_;
  wire _1_;
  wire _2_;
  (* src = "memory.v:5.7-5.11" *)
  input ADDR;
  wire ADDR;
  (* src = "memory.v:5.12-5.15" *)
  input CLK;
  wire CLK;
  (* src = "memory.v:6.22-6.25" *)
  input DIN;
  wire DIN;
  (* src = "memory.v:7.27-7.31" *)
  output DOUT;
  reg DOUT;
  reg \mem[0] ;
  reg \mem[1] ;
  INVX1 _3_ (
    .A(\mem[0] ),
    .Y(_1_)
  );
  NAND2X1 _4_ (
    .A(\mem[1] ),
    .B(ADDR),
    .Y(_2_)
  );
  OAI21X1 _5_ (
    .A(_1_),
    .B(ADDR),
    .C(_2_),
    .Y(_0_)
  );
  always @(posedge CLK)
    if (!ADDR) \mem[0]  <= DIN;
  always @(posedge CLK)
    DOUT <= _0_;
  always @(posedge CLK)
    if (ADDR) \mem[1]  <= DIN;
endmodule