@FIR-446: Zephyr on SKYLP (#12)

* @FIR-446: Zephyr on SKYLP This commit brings changes necessary to support SKYLP on Zephyr. It also makes changes necessary to support mulitple boards. In addition, the structure is customized for TSI SOCs. * Reverting print string so that sanity is not affected. --------- Co-authored-by: Riaz Khan <riaz@tsavoritesi.com>
tsisw · Jan 6, 2025 · ef6d74e · ef6d74e
1 parent 76b7bb2
commit ef6d74e
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diff --git a/boards/tsi/skylp/Kconfig b/boards/tsi/skylp/Kconfig
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+# config BOARD_TSI
+# 	select QEMU_TARGET
diff --git a/boards/tsi/skylp/Kconfig.defconfig b/boards/tsi/skylp/Kconfig.defconfig
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_TSI_SKYLP
+
+# MPU-based null-pointer dereferencing detection cannot
+# be applied as the (0x0 - 0x400) is unmapped but QEMU
+# will still permit bus access.
+choice NULL_POINTER_EXCEPTION_DETECTION
+	bool
+	default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET
+endchoice
+
+if SERIAL
+
+config UART_INTERRUPT_DRIVEN
+	default n
+
+endif # SERIAL
+
+endif
diff --git a/boards/tsi/skylp/Kconfig.tsi_skylp b/boards/tsi/skylp/Kconfig.tsi_skylp
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_TSI_SKYLP
+	select SOC_SKYLP_M85
diff --git a/boards/tsi/skylp/board.yml b/boards/tsi/skylp/board.yml
@@ -0,0 +1,10 @@
+board:
+  name: tsi_skylp
+  vendor: tsi
+  socs:
+  - name: skylp
+    variants:
+    - name: tensilica
+      cpucluster: txe
+    - name: cortex-m85
+      cpucluster: m85
diff --git a/boards/tsi/skylp/tsi_skylp_m85-common.dtsi b/boards/tsi/skylp/tsi_skylp_m85-common.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019-2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ sysclk: system-clock {
+	compatible = "fixed-clock";
+	clock-frequency = <25000000>;
+	#clock-cells = <0>;
+};
+
+uart0: uart@14001000 {
+	compatible = "arm,cmsdk-uart";
+	reg = <0x14001000 0x1000>;
+	interrupts = <34 3 33 3>;
+	interrupt-names = "tx", "rx";
+	clocks = <&sysclk>;
+	current-speed = <115200>;
+};
diff --git a/boards/tsi/skylp/tsi_skylp_m85.dts b/boards/tsi/skylp/tsi_skylp_m85.dts
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2024 TSI
+ * Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm/armv8.1-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <mem.h>
+
+/ {
+	compatible = "arm,mps3-an547";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &jtag_uart;
+		zephyr,shell-uart = &jtag_uart;
+		zephyr,sram = &sram;
+		zephyr,flash = &sram0;
+	};
+
+	jtag_uart: uart@86003000 {
+		compatible = "altr,jtag-uart";
+		reg = <0x86003000 0x8>;
+		status = "enabled";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m85";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8.1m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	/* We utilize the secure addresses, if you subtract 0x10000000
+	 * you'll get the non-secure alias
+	 */
+	itcm: itcm@4000 {   /* alias @ 0x4000 */
+		compatible = "zephyr,memory-region";
+		reg = <0x4000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	sram0: sram0@60000000 {	/* alias @ 0x60000000 */
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_K(256)>;
+		zephyr,memory-region = "SRAM0";
+	};
+
+	sram: sram@60040000 {	/* alias @ 0x60040000 */
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x60040000 DT_SIZE_K(1792)>;
+		zephyr,memory-region = "SRAM";
+	};
+
+	dtcm: dtcm@20000000 {	/* alias @ 0x20000000 */
+		compatible = "zephyr,memory-region";
+		reg = <0x20000000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	isram: sram@60200000 {/* alias @ 0x60200000, lower 1MB of 2 MB SRAM1 */
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x60200000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "ISRAM";
+	};
+
+	/* Higher 1 MB of 2MB high SRAM */
+	sram1: memory@60300000 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region";
+		reg = <0x60300000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "SRAM1";
+	};
+
+	/*soc {
+		peripheral@71000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x71000000 0x1effffff>;
+
+			 #include "tsi_skylp_m85-common.dtsi"
+		};
+	};*/
+};
+
+&jtag_uart {
+	status = "okay";
+	current-speed = <9600>;
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
diff --git a/boards/tsi/skylp/tsi_skylp_m85.yaml b/boards/tsi/skylp/tsi_skylp_m85.yaml
@@ -0,0 +1,12 @@
+identifier: tsi_skylp/m85
+name: TSI skylp
+type: mcu
+arch: arm
+ram: 1792
+flash: 256
+simulation: qemu
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+vendor: arm
diff --git a/boards/tsi/skylp/tsi_skylp_m85_defconfig b/boards/tsi/skylp/tsi_skylp_m85_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_RUNTIME_NMI=y
+CONFIG_ARM_TRUSTZONE_M=n
+CONFIG_ARM_MPU=y
+CONFIG_QEMU_ICOUNT_SHIFT=7
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+
+# Build a Secure firmware image
+CONFIG_TRUSTED_EXECUTION_SECURE=n
+
+# Build the zephyr.hex and zephyrstrp.hex for FPGA
+CONFIG_BUILD_OUTPUT_TSV_STRIPPED_HEX=y
diff --git a/boards/tsi/skylp/tsi_skylp_txe.dts b/boards/tsi/skylp/tsi_skylp_txe.dts
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2021, 2023, 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imx8m.dtsi>
+#include <nxp/nxp_imx/mimx8ml8dvnlz-pinctrl.dtsi>
+
+/ {
+	model = "NXP i.MX 8MPLUS Audio DSP";
+	compatible = "nxp";
+
+	chosen {
+		//zephyr,sram = &sram0;
+		zephyr,sram = &sram_txe;
+
+		zephyr,console = &uart4;
+		zephyr,shell-uart = &uart4;
+	};
+	sram_txe: memory@60040000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x60040000 DT_SIZE_K(512)>;
+	};
+};
+
+&pinctrl {
+	uart4_default: uart4_default {
+		group0 {
+			pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
+				<&iomuxc_uart4_txd_uart_tx_uart4_tx>;
+			bias-pull-up;
+			slew-rate = "slow";
+			drive-strength = "x1";
+		};
+	};
+};
+
+&uart4 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart4_default>;
+	pinctrl-names = "default";
+};
diff --git a/boards/tsi/skylp/tsi_skylp_txe.yaml b/boards/tsi/skylp/tsi_skylp_txe.yaml
@@ -0,0 +1,16 @@
+identifier: tsi_skylp/txe
+name: TSI TXE
+type: mcu
+arch: xtensa
+toolchain:
+  - xcc
+  - xt-clang
+  - zephyr
+supported:
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - mcumgr
+vendor: nxp
diff --git a/boards/tsi/skylp/tsi_skylp_txe_defconfig b/boards/tsi/skylp/tsi_skylp_txe_defconfig
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# size of stack for initialization and main thread
+CONFIG_MAIN_STACK_SIZE=3072
+
+# enable logger
+CONFIG_LOG=y
+
+# no need for a "raw" binary zephyr/zephyr.bin in the build directory
+CONFIG_BUILD_OUTPUT_BIN=y
+CONFIG_BUILD_OUTPUT_HEX=y
+
+# enable uart driver
+CONFIG_SERIAL=y
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# console (remote proc console by default)
+CONFIG_CONSOLE=y
+
+# uart console (overrides remote proc console)
+CONFIG_UART_CONSOLE=y
+
+# enable pin controller
+CONFIG_PINCTRL=y
diff --git a/boards/tsi/skyp/Kconfig.defconfig b/boards/tsi/skyp/Kconfig.defconfig
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 TSI
 # SPDX-License-Identifier: Apache-2.0
 
-if BOARD_TSI
+if BOARD_TSI_SKYP
 
 # MPU-based null-pointer dereferencing detection cannot
 # be applied as the (0x0 - 0x400) is unmapped but QEMU

diff --git a/boards/tsi/skyp/Kconfig.tsi b/boards/tsi/skyp/Kconfig.tsi
diff --git a/boards/tsi/skyp/Kconfig.tsi_skyp b/boards/tsi/skyp/Kconfig.tsi_skyp
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_TSI_SKYP
+	select SOC_SKYP_M85
+#	select SOC_PART_NUMBER_MIMX8ML8DVNLZ
+#	select SOC_SKYP_M85 if BOARD_TSI_SKYP_M85
+#	select SOC_MIMX8ML8_ADSP if BOARD_TSI_SKYP_TXE
diff --git a/boards/tsi/skyp/board.yml b/boards/tsi/skyp/board.yml
@@ -1,5 +1,5 @@
 board:
-  name: tsi
+  name: tsi_skyp
   vendor: tsi
   socs:
   - name: skyp

diff --git a/boards/tsi/skyp/tsi_skyp_m85.yaml b/boards/tsi/skyp/tsi_skyp_m85.yaml
@@ -1,5 +1,5 @@
-identifier: tsi/skyp/m85
-name: TSI sky-p
+identifier: tsi_skyp/m85
+name: TSI skyp
 type: mcu
 arch: arm
 ram: 1792

diff --git a/boards/tsi/skyp/tsi_skyp_txe.yaml b/boards/tsi/skyp/tsi_skyp_txe.yaml
@@ -1,4 +1,4 @@
-identifier: tsi/skyp/txe
+identifier: tsi_skyp/txe
 name: TSI DSP
 type: mcu
 arch: xtensa

diff --git a/soc/tsi/skylp_v1/CMakeLists.txt b/soc/tsi/skylp_v1/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  )
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/tsi/skylp_v1/Kconfig b/soc/tsi/skylp_v1/Kconfig
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_SKYLP_V1
+	select ARM
+
+config SOC_SERIES_SKYLP_V1
+	select CPU_CORTEX_M85
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select ARMV8_1_M_MVEI
+	select ARMV8_1_M_MVEF
+	select ARMV8_1_M_PMU
+
+config ARMV8_1_M_PMU_EVENTCNT
+	int
+	default 8 if SOC_SERIES_SKYLP_V1
diff --git a/soc/tsi/skylp_v1/Kconfig.defconfig b/soc/tsi/skylp_v1/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_SKYLP_V1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 25000000
+
+config NUM_IRQS
+	default 128
+
+endif # SOC_SERIES_SKYLP_V1