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Cor 315 (#16)
These patches ass COrstone315 support in MPS4. Corstone 315 is a M85 based board.
2 parents b9cde68 + e4df5b1 commit f233f6f

19 files changed

+353
-5
lines changed

‎boards/arm/mps4/Kconfig.defconfig‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
22
# SPDX-License-Identifier: Apache-2.0
33

4-
if BOARD_MPS4_CORSTONE320_FVP
4+
if BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE315_FVP
55

66
if SERIAL
77

@@ -10,7 +10,7 @@ config UART_INTERRUPT_DRIVEN
1010

1111
endif # SERIAL
1212

13-
if ROMSTART_RELOCATION_ROM && BOARD_MPS4_CORSTONE320_FVP
13+
if ROMSTART_RELOCATION_ROM && (BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE315_FVP)
1414

1515
config ROMSTART_REGION_ADDRESS
1616
default $(dt_nodelabel_reg_addr_hex,itcm)

‎boards/arm/mps4/Kconfig.mps4‎

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Original file line numberDiff line numberDiff line change
@@ -4,3 +4,4 @@
44
config BOARD_MPS4
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select SOC_SERIES_MPS4
66
select SOC_MPS4_CORSTONE320 if BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE320_FVP_NS
7+
select SOC_MPS4_CORSTONE315 if BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE315_FVP_NS

‎boards/arm/mps4/board.cmake‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,12 @@
1010
if(CONFIG_BOARD_MPS4_CORSTONE320_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP_NS)
1111
set(SUPPORTED_EMU_PLATFORMS armfvp)
1212
set(ARMFVP_BIN_NAME FVP_Corstone_SSE-320)
13-
if(CONFIG_BOARD_MPS4_CORSTONE320_FVP)
13+
elseif(CONFIG_BOARD_MPS4_CORSTONE315_FVP OR CONFIG_BOARD_MPS4_CORSTONE315_FVP_NS)
14+
set(SUPPORTED_EMU_PLATFORMS armfvp)
15+
set(ARMFVP_BIN_NAME FVP_Corstone_SSE-315)
16+
endif()
17+
18+
if(CONFIG_BOARD_MPS4_CORSTONE320_FVP OR CONFIG_BOARD_MPS4_CORSTONE315_FVP)
1419
set(ARMFVP_FLAGS
1520
# default is '0x11000000' but should match cpu<i>.INITSVTOR which is 0.
1621
-C mps4_board.subsystem.iotss3_systemcontrol.INITSVTOR_RST=0
@@ -19,7 +24,6 @@ if(CONFIG_BOARD_MPS4_CORSTONE320_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP_NS)
1924
# few MPU tests to fail.
2025
-C mps4_board.subsystem.cpu0.MPU_S=16
2126
)
22-
endif()
2327
endif()
2428

2529
if(CONFIG_BUILD_WITH_TFM)

‎boards/arm/mps4/board.yml‎

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Original file line numberDiff line numberDiff line change
@@ -8,3 +8,8 @@ board:
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- name: 'fvp'
99
variants:
1010
- name: 'ns'
11+
- name: 'corstone315'
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variants:
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- name: 'fvp'
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variants:
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- name: 'ns'

‎boards/arm/mps4/mps4_corstone315_fvp.dts‎

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1+
/*
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* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: Apache-2.0
5+
*/
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7+
/dts-v1/;
8+
9+
#include <arm/armv8.1-m.dtsi>
10+
#include <zephyr/dt-bindings/i2c/i2c.h>
11+
#include <zephyr/dt-bindings/input/input-event-codes.h>
12+
#include <mem.h>
13+
14+
/ {
15+
compatible = "arm,mps4-fvp";
16+
#address-cells = <1>;
17+
#size-cells = <1>;
18+
19+
chosen {
20+
zephyr,console = &uart0;
21+
zephyr,shell-uart = &uart0;
22+
zephyr,sram = &sram;
23+
zephyr,flash = &isram;
24+
};
25+
26+
cpus {
27+
#address-cells = <1>;
28+
#size-cells = <0>;
29+
30+
cpu@0 {
31+
device_type = "cpu";
32+
compatible = "arm,cortex-m85";
33+
reg = <0>;
34+
#address-cells = <1>;
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#size-cells = <1>;
36+
37+
mpu: mpu@e000ed90 {
38+
compatible = "arm,armv8.1m-mpu";
39+
reg = <0xe000ed90 0x40>;
40+
};
41+
};
42+
};
43+
44+
ethosu {
45+
#address-cells = <1>;
46+
#size-cells = <0>;
47+
interrupt-parent = <&nvic>;
48+
49+
ethosu0: ethosu@50004000 {
50+
compatible = "arm,ethos-u";
51+
reg = <0x50004000>;
52+
interrupts = <16 3>;
53+
secure-enable;
54+
privilege-enable;
55+
status = "okay";
56+
};
57+
};
58+
59+
/* We utilize the secure addresses, if you subtract 0x10000000
60+
* you'll get the non-secure alias
61+
*/
62+
itcm: itcm@10000000 { /* alias @ 0x0 */
63+
compatible = "zephyr,memory-region";
64+
reg = <0x10000000 DT_SIZE_K(32)>;
65+
zephyr,memory-region = "ITCM";
66+
};
67+
68+
sram: sram@12000000 { /* alias @ 0x01000000 */
69+
compatible = "zephyr,memory-region", "mmio-sram";
70+
reg = <0x12000000 DT_SIZE_M(2)>;
71+
zephyr,memory-region = "SRAM";
72+
};
73+
74+
dtcm: dtcm@30000000 { /* alias @ 0x20000000 */
75+
compatible = "zephyr,memory-region";
76+
reg = <0x30000000 DT_SIZE_K(32)>;
77+
zephyr,memory-region = "DTCM";
78+
};
79+
80+
isram: sram@31000000 { /* alias @ 0x21000000 */
81+
compatible = "zephyr,memory-region", "mmio-sram";
82+
reg = <0x31000000 DT_SIZE_M(4)>;
83+
zephyr,memory-region = "ISRAM";
84+
};
85+
86+
soc {
87+
peripheral@50000000 {
88+
#address-cells = <1>;
89+
#size-cells = <1>;
90+
ranges = <0x0 0x50000000 0x10000000>;
91+
92+
#include "mps4_common_soc_peripheral.dtsi"
93+
};
94+
};
95+
};
96+
97+
#include "mps4_common.dtsi"

‎boards/arm/mps4/mps4_corstone315_fvp.yaml‎

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1+
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
identifier: mps4/corstone315/fvp
5+
name: Arm MPS4-Corstone315-FVP
6+
type: mcu
7+
arch: arm
8+
ram: 2048
9+
flash: 4096
10+
simulation:
11+
- name: armfvp
12+
exec: FVP_Corstone_SSE-315
13+
toolchain:
14+
- gnuarmemb
15+
- zephyr
16+
supported:
17+
- gpio
18+
testing:
19+
default: true
20+
timeout_multiplier: 4
21+
ignore_tags:
22+
- drivers
23+
- bluetooth
24+
- net
25+
- timer
26+
vendor: arm

‎boards/arm/mps4/mps4_corstone315_fvp_defconfig‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
CONFIG_RUNTIME_NMI=y
5+
CONFIG_ARM_TRUSTZONE_M=y
6+
CONFIG_ARM_MPU=y
7+
8+
# GPIOs
9+
CONFIG_GPIO=y
10+
11+
# Serial
12+
CONFIG_CONSOLE=y
13+
CONFIG_UART_CONSOLE=y
14+
CONFIG_SERIAL=y
15+
16+
# Build a Secure firmware image
17+
CONFIG_TRUSTED_EXECUTION_SECURE=y
18+
# ROMSTART_REGION address and size are defined in Kconfig.defconfig
19+
CONFIG_ROMSTART_RELOCATION_ROM=y

‎boards/arm/mps4/mps4_corstone315_fvp_ns.dts‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,102 @@
1+
/*
2+
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/dts-v1/;
8+
9+
#include <arm/armv8.1-m.dtsi>
10+
#include <zephyr/dt-bindings/i2c/i2c.h>
11+
#include <zephyr/dt-bindings/input/input-event-codes.h>
12+
#include <mem.h>
13+
14+
/ {
15+
compatible = "arm,mps4-fvp";
16+
#address-cells = <1>;
17+
#size-cells = <1>;
18+
19+
chosen {
20+
zephyr,console = &uart0;
21+
zephyr,shell-uart = &uart0;
22+
zephyr,sram = &ram;
23+
zephyr,flash = &code;
24+
};
25+
26+
cpus {
27+
#address-cells = <1>;
28+
#size-cells = <0>;
29+
30+
cpu@0 {
31+
device_type = "cpu";
32+
compatible = "arm,cortex-m85";
33+
reg = <0>;
34+
#address-cells = <1>;
35+
#size-cells = <1>;
36+
37+
mpu: mpu@e000ed90 {
38+
compatible = "arm,armv8.1m-mpu";
39+
reg = <0xe000ed90 0x40>;
40+
};
41+
};
42+
};
43+
44+
/* We utilize the secure addresses, if you subtract 0x10000000
45+
* you'll get the non-secure alias
46+
*/
47+
itcm: itcm@0 {
48+
compatible = "zephyr,memory-region";
49+
reg = <0x0 DT_SIZE_K(32)>;
50+
zephyr,memory-region = "ITCM";
51+
};
52+
53+
sram: sram@1000000 {
54+
compatible = "zephyr,memory-region", "mmio-sram";
55+
reg = <0x1000000 DT_SIZE_M(2)>;
56+
zephyr,memory-region = "SRAM";
57+
};
58+
59+
dtcm: dtcm@20000000 {
60+
compatible = "zephyr,memory-region";
61+
reg = <0x20000000 DT_SIZE_K(512)>;
62+
zephyr,memory-region = "DTCM";
63+
};
64+
65+
isram: sram@21000000 {
66+
compatible = "zephyr,memory-region", "mmio-sram";
67+
reg = <0x21000000 DT_SIZE_M(4)>;
68+
zephyr,memory-region = "ISRAM";
69+
};
70+
71+
reserved-memory {
72+
#address-cells = <1>;
73+
#size-cells = <1>;
74+
ranges;
75+
76+
/* The memory regions defined below must match what the TF-M
77+
* project has defined for that board - a single image boot is
78+
* assumed. Please see the memory layout in:
79+
* https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps4/corstone320/common/partition/flash_layout.h
80+
*/
81+
82+
code: memory@28080000 {
83+
reg = <0x28080000 DT_SIZE_K(512)>;
84+
};
85+
86+
ram: memory@21020000 {
87+
reg = <0x21020000 DT_SIZE_M(1)>;
88+
};
89+
};
90+
91+
soc {
92+
peripheral@40000000 {
93+
#address-cells = <1>;
94+
#size-cells = <1>;
95+
ranges = <0x0 0x40000000 0x10000000>;
96+
97+
#include "mps4_common_soc_peripheral.dtsi"
98+
};
99+
};
100+
};
101+
102+
#include "mps4_common.dtsi"

‎boards/arm/mps4/mps4_corstone315_fvp_ns.yaml‎

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Original file line numberDiff line numberDiff line change
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1+
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
identifier: mps4/corstone315/fvp/ns
5+
name: Arm MPS4-Corstone315-FVP_ns
6+
type: mcu
7+
arch: arm
8+
ram: 1024
9+
flash: 512
10+
toolchain:
11+
- gnuarmemb
12+
- zephyr
13+
testing:
14+
only_tags:
15+
- trusted-firmware-m

‎boards/arm/mps4/mps4_corstone315_fvp_ns_defconfig‎

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1+
# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
CONFIG_ARM_TRUSTZONE_M=y
5+
CONFIG_RUNTIME_NMI=y
6+
CONFIG_ARM_MPU=y
7+
8+
# GPIOs
9+
CONFIG_GPIO=y
10+
11+
# Serial
12+
CONFIG_CONSOLE=y
13+
CONFIG_UART_CONSOLE=y
14+
CONFIG_SERIAL=y
15+
16+
# Build a Non-secure firmware image
17+
CONFIG_TRUSTED_EXECUTION_SECURE=n
18+
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
19+
CONFIG_BUILD_WITH_TFM=y

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