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XCoreVMem.core_desc
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XCoreVMem.core_desc
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import "../rv_base/RISCVBase.core_desc"
InstructionSet XCoreVMem extends RISCVBase {
instructions {
// ?
CV_LB_ri_inc {
encoding: imm12[11:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011;
assembly: {"cv.lb", "{name(rd)}, {imm12}({name(rs1)}!)"};
behavior: {
unsigned<XLEN> load_address = X[rs1];
signed<8> res = (signed<8>)MEM[load_address];
if (rd != 0) X[rd] = (unsigned<XLEN>)res;
X[rs1] += (signed)imm12;
}
}
CV_LBU_ri_inc {
encoding: imm12[11:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b0001011;
assembly: {"cv.lbu", "{name(rd)}, {imm12}({name(rs1)}!)"};
behavior: {
unsigned<XLEN> load_address = X[rs1];
unsigned<8> res = (unsigned<8>)MEM[load_address];
if (rd != 0) X[rd] = (unsigned<XLEN>)res;
X[rs1] += (signed)imm12;
}
}
CV_LH_ri_inc {
encoding: imm12[11:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0001011;
assembly: {"cv.lh", "{name(rd)}, {imm12}({name(rs1)}!)"};
behavior: {
unsigned<XLEN> load_address = X[rs1];
signed<16> res = (signed<16>)MEM[load_address];
if (rd != 0) X[rd] = (unsigned<XLEN>)res;
X[rs1] += (signed)imm12;
}
}
CV_LHU_ri_inc {
encoding: imm12[11:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0001011;
assembly: {"cv.lhu", "{name(rd)}, {imm12}({name(rs1)}!)"};
behavior: {
unsigned<XLEN> load_address = X[rs1];
unsigned<16> res = (unsigned<16>)MEM[load_address];
if (rd != 0) X[rd] = (unsigned<XLEN>)res;
X[rs1] += (signed)imm12;
}
}
CV_LW_ri_inc {
encoding: imm12[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0001011;
assembly: {"cv.lw", "{name(rd)}, {imm12}({name(rs1)}!)"};
behavior: {
unsigned<XLEN> load_address = X[rs1];
signed<32> res = (signed<32>)MEM[load_address];
if (rd != 0) X[rd] = (unsigned<XLEN>)res;
X[rs1] += (signed)imm12;
}
}
CV_LB_rr_inc {
encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: {"cv.lb", "{name(rd)}, {name(rs2)}({name(rs1)})"};
behavior: {
unsigned<XLEN> load_address = X[rs1]; // TODO: signed?
signed<8> res = (signed<8>)MEM[load_address];
if(rd != 0) X[rd] = (unsigned<XLEN>)res;
X[rs1] += (signed)X[rs2];
}
}
CV_LBU_rr_inc {
encoding: 7'b0001000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: {"cv.lbu", "{name(rd)}, {name(rs2)}({name(rs1)})"};
behavior: {
unsigned<XLEN> load_address = X[rs1]; // TODO: signed?
unsigned<8> res = (unsigned<8>)MEM[load_address];
if(rd != 0) X[rd] = (unsigned<XLEN>)res;
X[rs1] += (signed)X[rs2];
}
}
CV_LH_rr_inc {
encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: {"cv.lh", "{name(rd)}, {name(rs2)}({name(rs1)})"};
behavior: {
unsigned<XLEN> load_address = X[rs1]; // TODO: signed?
signed<16> res = (signed<16>)MEM[load_address];
if(rd != 0) X[rd] = (unsigned<XLEN>)res;
X[rs1] += (signed)X[rs2];
}
}
CV_LHU_rr_inc {
encoding: 7'b0001001 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: {"cv.lhu", "{name(rd)}, {name(rs2)}({name(rs1)})"};
behavior: {
unsigned<XLEN> load_address = X[rs1]; // TODO: signed?
unsigned<16> res = (unsigned<16>)MEM[load_address];
if(rd != 0) X[rd] = (unsigned<XLEN>)res;
X[rs1] += (signed)X[rs2];
}
}
CV_LW_rr_inc {
encoding: 7'b0000010 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: {"cv.lw", "{name(rd)}, {name(rs2)}({name(rs1)})"};
behavior: {
unsigned<XLEN> load_address = X[rs1]; // TODO: signed?
signed<32> res = (signed<32>)MEM[load_address];
if(rd != 0) X[rd] = (unsigned<XLEN>)res;
X[rs1] += (signed)X[rs2];
}
}
CV_LB_rr {
encoding: 7'b0000100 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: {"cv.lb", "{name(rd)}, {name(rs2)}({name(rs1)})"};
behavior: {
unsigned<XLEN> load_address = X[rs1] + X[rs2]; // TODO: signed?
signed<8> res = (signed<8>)MEM[load_address];
if(rd != 0) X[rd] = (unsigned<XLEN>)res;
}
}
CV_LBU_rr {
encoding: 7'b0001100 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: {"cv.lbu", "{name(rd)}, {name(rs2)}({name(rs1)})"};
behavior: {
unsigned<XLEN> load_address = X[rs1] + X[rs2]; // TODO: signed?
unsigned<8> res = (unsigned<8>)MEM[load_address];
if(rd != 0) X[rd] = (unsigned<XLEN>)res;
}
}
CV_LH_rr {
encoding: 7'b0000101 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: {"cv.lh", "{name(rd)}, {name(rs2)}({name(rs1)})"};
behavior: {
unsigned<XLEN> load_address = X[rs1] + X[rs2]; // TODO: signed?
signed<16> res = (signed<16>)MEM[load_address];
if(rd != 0) X[rd] = (unsigned<XLEN>)res;
}
}
CV_LHU_rr {
encoding: 7'b0001101 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: {"cv.lhu", "{name(rd)}, {name(rs2)}({name(rs1)})"};
behavior: {
unsigned<XLEN> load_address = X[rs1] + X[rs2]; // TODO: signed?
unsigned<16> res = (unsigned<16>)MEM[load_address];
if(rd != 0) X[rd] = (unsigned<XLEN>)res;
}
}
CV_LW_rr {
encoding: 7'b0000110 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
assembly: {"cv.lh", "{name(rd)}, {name(rs2)}({name(rs1)})"};
behavior: {
unsigned<XLEN> load_address = X[rs1] + X[rs2]; // TODO: signed?
signed<32> res = (signed<32>)MEM[load_address];
if(rd != 0) X[rd] = (unsigned<XLEN>)res;
}
}
CV_SB_ri_inc {
encoding: imm12[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: imm12[4:0] :: 7'b0101011;
assembly: {"cv.sb", "{name(rs2)}, {imm12}({name(rs1)}!)"};
behavior: {
unsigned<XLEN> store_address = X[rs1];
MEM[store_address] = (signed<8>)X[rs2];
X[rs1] += (signed)imm12;
}
}
CV_SH_ri_inc {
encoding: imm12[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: imm12[4:0] :: 7'b0101011;
assembly: {"cv.sh", "{name(rs2)}, {imm12}({name(rs1)}!)"};
behavior: {
unsigned<XLEN> store_address = X[rs1];
MEM[store_address] = (signed<16>)X[rs2];
X[rs1] += (signed)imm12;
}
}
CV_SW_ri_inc {
encoding: imm12[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: imm12[4:0] :: 7'b0101011;
assembly: {"cv.sw", "{name(rs2)}, {imm12}({name(rs1)}!)"};
behavior: {
unsigned<XLEN> store_address = X[rs1];
MEM[store_address] = (signed<32>)X[rs2];
X[rs1] += (signed)imm12;
}
}
CV_SB_rr_inc {
encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rs3[4:0] :: 7'b0101011;
assembly: {"cv.sb", "{name(rs2)}, {name(rs3)}({name(rs1)})"};
behavior: {
unsigned<XLEN> store_address = X[rs1]; // TODO: signed?
MEM[store_address] = (signed<8>)X[rs2];
X[rs1] += (signed)X[rs3];
}
}
CV_SH_rr_inc {
encoding: 7'b0010001 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rs3[4:0] :: 7'b0101011;
assembly: {"cv.sh", "{name(rs2)}, {name(rs3)}({name(rs1)})"};
behavior: {
unsigned<XLEN> store_address = X[rs1]; // TODO: signed?
MEM[store_address] = (signed<16>)X[rs2];
X[rs1] += (signed)X[rs3];
}
}
CV_SW_rr_inc {
encoding: 7'b0010010 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rs3[4:0] :: 7'b0101011;
assembly: {"cv.sw", "{name(rs2)}, {name(rs3)}({name(rs1)})"};
behavior: {
unsigned<XLEN> store_address = X[rs1]; // TODO: signed?
MEM[store_address] = (signed<32>)X[rs2];
X[rs1] += (signed)X[rs3];
}
}
CV_SB_rr {
encoding: 7'b0010100 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rs3[4:0] :: 7'b0101011;
assembly: {"cv.sb", "{name(rs2)}, {name(rs3)}({name(rs1)})"};
behavior: {
unsigned<XLEN> store_address = X[rs1] + X[rs3]; // TODO: signed?
MEM[store_address] = (signed<8>)X[rs2];
}
}
CV_SH_rr {
encoding: 7'b0010101 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rs3[4:0] :: 7'b0101011;
assembly: {"cv.sh", "{name(rs2)}, {name(rs3)}({name(rs1)})"};
behavior: {
unsigned<XLEN> store_address = X[rs1] + X[rs3]; // TODO: signed?
MEM[store_address] = (signed<16>)X[rs2];
}
}
CV_SW_rr {
encoding: 7'b0010110 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rs3[4:0] :: 7'b0101011;
assembly: {"cv.sw", "{name(rs2)}, {name(rs3)}({name(rs1)})"};
behavior: {
unsigned<XLEN> store_address = X[rs1] + X[rs3]; // TODO: signed?
MEM[store_address] = (signed<32>)X[rs2];
}
}
}
}