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Improve documentation for SSDTs #174
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@PhantomR I can update the docs with a basic explaination. But the majority of what is done is already explained here: https://osy.gitbook.io/hac-mini-guide/details/thunderbolt-3-fix You'll have to be familiar with reading ASL source code and understanding it. The majority of the patch is just enumerating the controller. See https://github.com/tylernguyen/x1c6-hackintosh/blob/main/ACPI/Disassembled%20ACPI/BIOS-v1.43/SSDT-7-TbtTypeC.dsl for the way it's originally enumerated. The other part of the patch is just USB mapping. You'll occasionally see debug hooks in the patch, these are in there during the patch process in order to determine the specific event when they happen. If you want to adapt the patch to your machine:
NOTE that the way the patches are done here: EDIT: You'll need an understanding of ASL source to read/write patches. See https://acpica.org/sites/acpica/files/asl_tutorial_v20190625.pdf for a tutorial/ref of ASL. |
I really hope this is not too much to ask as I know you are doing us all a favor by sharing this, @tylernguyen , but would it be possible to add a few more explanations as to what the SSDTs XHC1, XHC2, SSDT-TB3, along with each of the TB-DSB* actually do? More precisely, what do you mean by fixing USB 3.1 (associated with the TB-DSBs) and fixing USB power management (XHC1)?
I am mainly interested in them because I would like to know how I could adapt them for an X1 Yoga Gen3.
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