Question: what's the state and next step for this new feature?

[aledbf]

Thank you for adding this new feature.
I was wondering if there's a way to track the status of it. I haven't seen any updates in the mailing list thread.
Thanks!

[laijs]

@aledbf I'm glad that you are interested in it. Thank you too.

We have been fixing some problems (from this github issues, private emails, and internal reviews/testings).

We are going to push the effort to make the Linux kernel PIE and fix the problem of the x86 entry code which PVM is highly dependent on. We may send the V2 patchset along the way.

[aledbf]

@laijs just one question, it seems I'm missing something to get more than one core? Testing on an Amazon EC2 c6i.8xlarge with --cpus boot=8

cat /proc/cpuinfo 
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 106
model name      : Intel(R) Xeon(R) Platinum 8375C CPU @ 2.90GHz
stepping        : 6
microcode       : 0x1
cpu MHz         : 2899.952
cache size      : 55296 KB
physical id     : 0
siblings        : 1
core id         : 0
cpu cores       : 1
apicid          : 0
initial apicid  : 0
fpu             : yes
fpu_exception   : yes
cpuid level     : 27
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ss syscall nx pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid tsc_known_freq pni pclmulqdq ssse3 fma cx16 pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand hypervisor lahf_lm abm 3dnowprefetch pti ssbd ibpb stibp ibrs_enhanced kvm_pvm_guest fsgsbase tsc_adjust bmi1 avx2 bmi2 erms invpcid avx512f avx512dq rdseed adx avx512ifma clflushopt clwb avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 wbnoinvd arat avx512vbmi avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq rdpid md_clear flush_l1d arch_capabilities
bugs            : spectre_v1 spectre_v2 spec_store_bypass swapgs mmio_stale_data eibrs_pbrsb gds
bogomips        : 5799.90
clflush size    : 64
cache_alignment : 64
address sizes   : 46 bits physical, 48 bits virtual
power management:

[aledbf]

Testing firecracker I see the right number of cores.

[laijs]

@aledbf Thank you for the test.

Has the problem been fixed? what was the VMM?

[aledbf]

@laijs firecracker works as expected, except for restoring a snapshot. Besides this detail, it just works.

I have one question: what's the performance "penalty" for using PVM?
Thanks!

[laijs]

@aledbf

The most significant drawback of PVM is shadowpaging. Shadowpaging
results in very bad performance when guest applications frequently
modify pagetable, including excessive processes forking.

[bysui]

@laijs firecracker works as expected, except for restoring a snapshot. Besides this detail, it just works.

I have one question: what's the performance "penalty" for using PVM? Thanks!

Hi @aledbf, is this related to the problem mentioned in #2 (comment) ?
Firecracker doesn't save/restore PVM MSRs.

[aledbf]

@bysui yes, exactly that. Thanks. I will test firecracker with the change 🙏