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Configurable GPIO option ARCH_NR_GPIO for x86 architecture (sonic-net#232)
The x86 platform did not allow configuring the maximum number of GPIOs
supported, although the ARM platform did. For cisco-8000 platform,
each FPGA gpio IP block can support 1K pins. Distributed chassis with
Route processor and Fabric card can have 10 such IP blocks, along with
additional pins through i2c gpio extenders.
This patch supports configurable number of GPIO's at kernel config time
similar to ARM platform.
Signed-off-by: Madhava Reddy Siddareddygari <msiddare@cisco.com>
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