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1 parent ee5fd49 commit 8831315Copy full SHA for 8831315
vllm/v1/core/sched/output.py
@@ -6,7 +6,7 @@
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from dataclasses import dataclass
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from typing import TYPE_CHECKING, Optional
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-from vllm import bc_linter_include
+from vllm._bc_linter import bc_linter_include
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if TYPE_CHECKING:
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import numpy as np
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