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MipsAsmParser.cpp
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//===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/MipsABIFlagsSection.h"
#include "MCTargetDesc/MipsABIInfo.h"
#include "MCTargetDesc/MipsBaseInfo.h"
#include "MCTargetDesc/MipsMCExpr.h"
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "MipsTargetStreamer.h"
#include "TargetInfo/MipsTargetInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCObjectFileInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCAsmParserExtension.h"
#include "llvm/MC/MCParser/MCAsmParserUtils.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCSymbolELF.h"
#include "llvm/MC/MCValue.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Alignment.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/SMLoc.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/SubtargetFeature.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <memory>
#include <string>
#include <utility>
using namespace llvm;
#define DEBUG_TYPE "mips-asm-parser"
namespace llvm {
class MCInstrInfo;
} // end namespace llvm
extern cl::opt<bool> EmitJalrReloc;
namespace {
class MipsAssemblerOptions {
public:
MipsAssemblerOptions(const FeatureBitset &Features_) : Features(Features_) {}
MipsAssemblerOptions(const MipsAssemblerOptions *Opts) {
ATReg = Opts->getATRegIndex();
Reorder = Opts->isReorder();
Macro = Opts->isMacro();
Features = Opts->getFeatures();
}
unsigned getATRegIndex() const { return ATReg; }
bool setATRegIndex(unsigned Reg) {
if (Reg > 31)
return false;
ATReg = Reg;
return true;
}
bool isReorder() const { return Reorder; }
void setReorder() { Reorder = true; }
void setNoReorder() { Reorder = false; }
bool isMacro() const { return Macro; }
void setMacro() { Macro = true; }
void setNoMacro() { Macro = false; }
const FeatureBitset &getFeatures() const { return Features; }
void setFeatures(const FeatureBitset &Features_) { Features = Features_; }
// Set of features that are either architecture features or referenced
// by them (e.g.: FeatureNaN2008 implied by FeatureMips32r6).
// The full table can be found in MipsGenSubtargetInfo.inc (MipsFeatureKV[]).
// The reason we need this mask is explained in the selectArch function.
// FIXME: Ideally we would like TableGen to generate this information.
static const FeatureBitset AllArchRelatedMask;
private:
unsigned ATReg = 1;
bool Reorder = true;
bool Macro = true;
FeatureBitset Features;
};
} // end anonymous namespace
const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = {
Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit,
Mips::FeatureNaN2008
};
namespace {
class MipsAsmParser : public MCTargetAsmParser {
MipsTargetStreamer &getTargetStreamer() {
assert(getParser().getStreamer().getTargetStreamer() &&
"do not have a target streamer");
MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
return static_cast<MipsTargetStreamer &>(TS);
}
MipsABIInfo ABI;
SmallVector<std::unique_ptr<MipsAssemblerOptions>, 2> AssemblerOptions;
MCSymbol *CurrentFn; // Pointer to the function being parsed. It may be a
// nullptr, which indicates that no function is currently
// selected. This usually happens after an '.end func'
// directive.
bool IsLittleEndian;
bool IsPicEnabled;
bool IsCpRestoreSet;
int CpRestoreOffset;
unsigned GPReg;
unsigned CpSaveLocation;
/// If true, then CpSaveLocation is a register, otherwise it's an offset.
bool CpSaveLocationIsRegister;
// Map of register aliases created via the .set directive.
StringMap<AsmToken> RegisterSets;
// Print a warning along with its fix-it message at the given range.
void printWarningWithFixIt(const Twine &Msg, const Twine &FixMsg,
SMRange Range, bool ShowColors = true);
void ConvertXWPOperands(MCInst &Inst, const OperandVector &Operands);
#define GET_ASSEMBLER_HEADER
#include "MipsGenAsmMatcher.inc"
unsigned
checkEarlyTargetMatchPredicate(MCInst &Inst,
const OperandVector &Operands) override;
unsigned checkTargetMatchPredicate(MCInst &Inst) override;
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
/// Parse a register as used in CFI directives
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool parseParenSuffix(StringRef Name, OperandVector &Operands);
bool parseBracketSuffix(StringRef Name, OperandVector &Operands);
bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override;
bool ParseDirective(AsmToken DirectiveID) override;
ParseStatus parseMemOperand(OperandVector &Operands);
ParseStatus matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
StringRef Identifier, SMLoc S);
ParseStatus matchAnyRegisterWithoutDollar(OperandVector &Operands,
const AsmToken &Token, SMLoc S);
ParseStatus matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S);
ParseStatus parseAnyRegister(OperandVector &Operands);
ParseStatus parseImm(OperandVector &Operands);
ParseStatus parseJumpTarget(OperandVector &Operands);
ParseStatus parseInvNum(OperandVector &Operands);
ParseStatus parseRegisterList(OperandVector &Operands);
bool searchSymbolAlias(OperandVector &Operands);
bool parseOperand(OperandVector &, StringRef Mnemonic);
enum MacroExpanderResultTy {
MER_NotAMacro,
MER_Success,
MER_Fail,
};
// Expands assembly pseudo instructions.
MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg,
bool Is32BitImm, bool IsAddress, SMLoc IDLoc,
MCStreamer &Out, const MCSubtargetInfo *STI);
bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
MCStreamer &Out, const MCSubtargetInfo *STI);
bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym);
bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
MCStreamer &Out, const MCSubtargetInfo *STI);
bool expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc,
MCStreamer &Out, const MCSubtargetInfo *STI);
bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
const MCOperand &Offset, bool Is32BitAddress,
SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
void expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI, bool IsLoad);
void expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI, bool IsLoad);
bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI, const bool IsMips64,
const bool Signed);
bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc,
MCStreamer &Out, const MCSubtargetInfo *STI);
bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandRotation(MCInst &Inst, SMLoc IDLoc,
MCStreamer &Out, const MCSubtargetInfo *STI);
bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI, bool IsLoad);
bool expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
bool reportParseError(const Twine &ErrorMsg);
bool reportParseError(SMLoc Loc, const Twine &ErrorMsg);
bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
bool parseSetMips0Directive();
bool parseSetArchDirective();
bool parseSetFeature(uint64_t Feature);
bool isPicAndNotNxxAbi(); // Used by .cpload, .cprestore, and .cpsetup.
bool parseDirectiveCpAdd(SMLoc Loc);
bool parseDirectiveCpLoad(SMLoc Loc);
bool parseDirectiveCpLocal(SMLoc Loc);
bool parseDirectiveCpRestore(SMLoc Loc);
bool parseDirectiveCPSetup();
bool parseDirectiveCPReturn();
bool parseDirectiveNaN();
bool parseDirectiveSet();
bool parseDirectiveOption();
bool parseInsnDirective();
bool parseRSectionDirective(StringRef Section);
bool parseSSectionDirective(StringRef Section, unsigned Type);
bool parseSetAtDirective();
bool parseSetNoAtDirective();
bool parseSetMacroDirective();
bool parseSetNoMacroDirective();
bool parseSetMsaDirective();
bool parseSetNoMsaDirective();
bool parseSetNoDspDirective();
bool parseSetNoMips3DDirective();
bool parseSetReorderDirective();
bool parseSetNoReorderDirective();
bool parseSetMips16Directive();
bool parseSetNoMips16Directive();
bool parseSetFpDirective();
bool parseSetOddSPRegDirective();
bool parseSetNoOddSPRegDirective();
bool parseSetPopDirective();
bool parseSetPushDirective();
bool parseSetSoftFloatDirective();
bool parseSetHardFloatDirective();
bool parseSetMtDirective();
bool parseSetNoMtDirective();
bool parseSetNoCRCDirective();
bool parseSetNoVirtDirective();
bool parseSetNoGINVDirective();
bool parseSetAssignment();
bool parseDirectiveGpWord();
bool parseDirectiveGpDWord();
bool parseDirectiveDtpRelWord();
bool parseDirectiveDtpRelDWord();
bool parseDirectiveTpRelWord();
bool parseDirectiveTpRelDWord();
bool parseDirectiveModule();
bool parseDirectiveModuleFP();
bool parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI,
StringRef Directive);
bool parseInternalDirectiveReallowModule();
bool eatComma(StringRef ErrorStr);
int matchCPURegisterName(StringRef Symbol);
int matchHWRegsRegisterName(StringRef Symbol);
int matchFPURegisterName(StringRef Name);
int matchFCCRegisterName(StringRef Name);
int matchACRegisterName(StringRef Name);
int matchMSA128RegisterName(StringRef Name);
int matchMSA128CtrlRegisterName(StringRef Name);
unsigned getReg(int RC, int RegNo);
/// Returns the internal register number for the current AT. Also checks if
/// the current AT is unavailable (set to $0) and gives an error if it is.
/// This should be used in pseudo-instruction expansions which need AT.
unsigned getATReg(SMLoc Loc);
bool canUseATReg();
bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
// Helper function that checks if the value of a vector index is within the
// boundaries of accepted values for each RegisterKind
// Example: INSERT.B $w0[n], $1 => 16 > n >= 0
bool validateMSAIndex(int Val, int RegKind);
// Selects a new architecture by updating the FeatureBits with the necessary
// info including implied dependencies.
// Internally, it clears all the feature bits related to *any* architecture
// and selects the new one using the ToggleFeature functionality of the
// MCSubtargetInfo object that handles implied dependencies. The reason we
// clear all the arch related bits manually is because ToggleFeature only
// clears the features that imply the feature being cleared and not the
// features implied by the feature being cleared. This is easier to see
// with an example:
// --------------------------------------------------
// | Feature | Implies |
// | -------------------------------------------------|
// | FeatureMips1 | None |
// | FeatureMips2 | FeatureMips1 |
// | FeatureMips3 | FeatureMips2 | FeatureMipsGP64 |
// | FeatureMips4 | FeatureMips3 |
// | ... | |
// --------------------------------------------------
//
// Setting Mips3 is equivalent to set: (FeatureMips3 | FeatureMips2 |
// FeatureMipsGP64 | FeatureMips1)
// Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4).
void selectArch(StringRef ArchFeature) {
MCSubtargetInfo &STI = copySTI();
FeatureBitset FeatureBits = STI.getFeatureBits();
FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
STI.setFeatureBits(FeatureBits);
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(ArchFeature)));
AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
}
void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
if (!(getSTI().hasFeature(Feature))) {
MCSubtargetInfo &STI = copySTI();
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
}
}
void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
if (getSTI().hasFeature(Feature)) {
MCSubtargetInfo &STI = copySTI();
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
}
}
void setModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
setFeatureBits(Feature, FeatureString);
AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
}
void clearModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
clearFeatureBits(Feature, FeatureString);
AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
}
public:
enum MipsMatchResultTy {
Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY,
Match_RequiresDifferentOperands,
Match_RequiresNoZeroRegister,
Match_RequiresSameSrcAndDst,
Match_NoFCCRegisterForCurrentISA,
Match_NonZeroOperandForSync,
Match_NonZeroOperandForMTCX,
Match_RequiresPosSizeRange0_32,
Match_RequiresPosSizeRange33_64,
Match_RequiresPosSizeUImm6,
#define GET_OPERAND_DIAGNOSTIC_TYPES
#include "MipsGenAsmMatcher.inc"
#undef GET_OPERAND_DIAGNOSTIC_TYPES
};
MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, sti, MII),
ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
sti.getCPU(), Options)) {
MCAsmParserExtension::Initialize(parser);
parser.addAliasForDirective(".asciiz", ".asciz");
parser.addAliasForDirective(".hword", ".2byte");
parser.addAliasForDirective(".word", ".4byte");
parser.addAliasForDirective(".dword", ".8byte");
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
// Remember the initial assembler options. The user can not modify these.
AssemblerOptions.push_back(
std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
// Create an assembler options environment for the user to modify.
AssemblerOptions.push_back(
std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
getTargetStreamer().updateABIInfo(*this);
if (!isABI_O32() && !useOddSPReg() != 0)
report_fatal_error("-mno-odd-spreg requires the O32 ABI");
CurrentFn = nullptr;
IsPicEnabled = getContext().getObjectFileInfo()->isPositionIndependent();
IsCpRestoreSet = false;
CpRestoreOffset = -1;
GPReg = ABI.GetGlobalPtr();
const Triple &TheTriple = sti.getTargetTriple();
IsLittleEndian = TheTriple.isLittleEndian();
if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode())
report_fatal_error("microMIPS64R6 is not supported", false);
if (!isABI_O32() && inMicroMipsMode())
report_fatal_error("microMIPS64 is not supported", false);
}
/// True if all of $fcc0 - $fcc7 exist for the current ISA.
bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
bool isGP64bit() const {
return getSTI().hasFeature(Mips::FeatureGP64Bit);
}
bool isFP64bit() const {
return getSTI().hasFeature(Mips::FeatureFP64Bit);
}
bool isJalrRelocAvailable(const MCExpr *JalExpr) {
if (!EmitJalrReloc)
return false;
MCValue Res;
if (!JalExpr->evaluateAsRelocatable(Res, nullptr, nullptr))
return false;
if (Res.getSymB() != nullptr)
return false;
if (Res.getConstant() != 0)
return ABI.IsN32() || ABI.IsN64();
return true;
}
const MipsABIInfo &getABI() const { return ABI; }
bool isABI_N32() const { return ABI.IsN32(); }
bool isABI_N64() const { return ABI.IsN64(); }
bool isABI_O32() const { return ABI.IsO32(); }
bool isABI_FPXX() const {
return getSTI().hasFeature(Mips::FeatureFPXX);
}
bool useOddSPReg() const {
return !(getSTI().hasFeature(Mips::FeatureNoOddSPReg));
}
bool inMicroMipsMode() const {
return getSTI().hasFeature(Mips::FeatureMicroMips);
}
bool hasMips1() const {
return getSTI().hasFeature(Mips::FeatureMips1);
}
bool hasMips2() const {
return getSTI().hasFeature(Mips::FeatureMips2);
}
bool hasMips3() const {
return getSTI().hasFeature(Mips::FeatureMips3);
}
bool hasMips4() const {
return getSTI().hasFeature(Mips::FeatureMips4);
}
bool hasMips5() const {
return getSTI().hasFeature(Mips::FeatureMips5);
}
bool hasMips32() const {
return getSTI().hasFeature(Mips::FeatureMips32);
}
bool hasMips64() const {
return getSTI().hasFeature(Mips::FeatureMips64);
}
bool hasMips32r2() const {
return getSTI().hasFeature(Mips::FeatureMips32r2);
}
bool hasMips64r2() const {
return getSTI().hasFeature(Mips::FeatureMips64r2);
}
bool hasMips32r3() const {
return (getSTI().hasFeature(Mips::FeatureMips32r3));
}
bool hasMips64r3() const {
return (getSTI().hasFeature(Mips::FeatureMips64r3));
}
bool hasMips32r5() const {
return (getSTI().hasFeature(Mips::FeatureMips32r5));
}
bool hasMips64r5() const {
return (getSTI().hasFeature(Mips::FeatureMips64r5));
}
bool hasMips32r6() const {
return getSTI().hasFeature(Mips::FeatureMips32r6);
}
bool hasMips64r6() const {
return getSTI().hasFeature(Mips::FeatureMips64r6);
}
bool hasDSP() const {
return getSTI().hasFeature(Mips::FeatureDSP);
}
bool hasDSPR2() const {
return getSTI().hasFeature(Mips::FeatureDSPR2);
}
bool hasDSPR3() const {
return getSTI().hasFeature(Mips::FeatureDSPR3);
}
bool hasMSA() const {
return getSTI().hasFeature(Mips::FeatureMSA);
}
bool hasCnMips() const {
return (getSTI().hasFeature(Mips::FeatureCnMips));
}
bool hasCnMipsP() const {
return (getSTI().hasFeature(Mips::FeatureCnMipsP));
}
bool inPicMode() {
return IsPicEnabled;
}
bool inMips16Mode() const {
return getSTI().hasFeature(Mips::FeatureMips16);
}
bool useTraps() const {
return getSTI().hasFeature(Mips::FeatureUseTCCInDIV);
}
bool useSoftFloat() const {
return getSTI().hasFeature(Mips::FeatureSoftFloat);
}
bool hasMT() const {
return getSTI().hasFeature(Mips::FeatureMT);
}
bool hasCRC() const {
return getSTI().hasFeature(Mips::FeatureCRC);
}
bool hasVirt() const {
return getSTI().hasFeature(Mips::FeatureVirt);
}
bool hasGINV() const {
return getSTI().hasFeature(Mips::FeatureGINV);
}
/// Warn if RegIndex is the same as the current AT.
void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
void warnIfNoMacro(SMLoc Loc);
bool isLittle() const { return IsLittleEndian; }
const MCExpr *createTargetUnaryExpr(const MCExpr *E,
AsmToken::TokenKind OperatorToken,
MCContext &Ctx) override {
switch(OperatorToken) {
default:
llvm_unreachable("Unknown token");
return nullptr;
case AsmToken::PercentCall16:
return MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, E, Ctx);
case AsmToken::PercentCall_Hi:
return MipsMCExpr::create(MipsMCExpr::MEK_CALL_HI16, E, Ctx);
case AsmToken::PercentCall_Lo:
return MipsMCExpr::create(MipsMCExpr::MEK_CALL_LO16, E, Ctx);
case AsmToken::PercentDtprel_Hi:
return MipsMCExpr::create(MipsMCExpr::MEK_DTPREL_HI, E, Ctx);
case AsmToken::PercentDtprel_Lo:
return MipsMCExpr::create(MipsMCExpr::MEK_DTPREL_LO, E, Ctx);
case AsmToken::PercentGot:
return MipsMCExpr::create(MipsMCExpr::MEK_GOT, E, Ctx);
case AsmToken::PercentGot_Disp:
return MipsMCExpr::create(MipsMCExpr::MEK_GOT_DISP, E, Ctx);
case AsmToken::PercentGot_Hi:
return MipsMCExpr::create(MipsMCExpr::MEK_GOT_HI16, E, Ctx);
case AsmToken::PercentGot_Lo:
return MipsMCExpr::create(MipsMCExpr::MEK_GOT_LO16, E, Ctx);
case AsmToken::PercentGot_Ofst:
return MipsMCExpr::create(MipsMCExpr::MEK_GOT_OFST, E, Ctx);
case AsmToken::PercentGot_Page:
return MipsMCExpr::create(MipsMCExpr::MEK_GOT_PAGE, E, Ctx);
case AsmToken::PercentGottprel:
return MipsMCExpr::create(MipsMCExpr::MEK_GOTTPREL, E, Ctx);
case AsmToken::PercentGp_Rel:
return MipsMCExpr::create(MipsMCExpr::MEK_GPREL, E, Ctx);
case AsmToken::PercentHi:
return MipsMCExpr::create(MipsMCExpr::MEK_HI, E, Ctx);
case AsmToken::PercentHigher:
return MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, E, Ctx);
case AsmToken::PercentHighest:
return MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, E, Ctx);
case AsmToken::PercentLo:
return MipsMCExpr::create(MipsMCExpr::MEK_LO, E, Ctx);
case AsmToken::PercentNeg:
return MipsMCExpr::create(MipsMCExpr::MEK_NEG, E, Ctx);
case AsmToken::PercentPcrel_Hi:
return MipsMCExpr::create(MipsMCExpr::MEK_PCREL_HI16, E, Ctx);
case AsmToken::PercentPcrel_Lo:
return MipsMCExpr::create(MipsMCExpr::MEK_PCREL_LO16, E, Ctx);
case AsmToken::PercentTlsgd:
return MipsMCExpr::create(MipsMCExpr::MEK_TLSGD, E, Ctx);
case AsmToken::PercentTlsldm:
return MipsMCExpr::create(MipsMCExpr::MEK_TLSLDM, E, Ctx);
case AsmToken::PercentTprel_Hi:
return MipsMCExpr::create(MipsMCExpr::MEK_TPREL_HI, E, Ctx);
case AsmToken::PercentTprel_Lo:
return MipsMCExpr::create(MipsMCExpr::MEK_TPREL_LO, E, Ctx);
}
}
bool areEqualRegs(const MCParsedAsmOperand &Op1,
const MCParsedAsmOperand &Op2) const override;
};
/// MipsOperand - Instances of this class represent a parsed Mips machine
/// instruction.
class MipsOperand : public MCParsedAsmOperand {
public:
/// Broad categories of register classes
/// The exact class is finalized by the render method.
enum RegKind {
RegKind_GPR = 1, /// GPR32 and GPR64 (depending on isGP64bit())
RegKind_FGR = 2, /// FGR32, FGR64, AFGR64 (depending on context and
/// isFP64bit())
RegKind_FCC = 4, /// FCC
RegKind_MSA128 = 8, /// MSA128[BHWD] (makes no difference which)
RegKind_MSACtrl = 16, /// MSA control registers
RegKind_COP2 = 32, /// COP2
RegKind_ACC = 64, /// HI32DSP, LO32DSP, and ACC64DSP (depending on
/// context).
RegKind_CCR = 128, /// CCR
RegKind_HWRegs = 256, /// HWRegs
RegKind_COP3 = 512, /// COP3
RegKind_COP0 = 1024, /// COP0
/// Potentially any (e.g. $1)
RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
RegKind_CCR | RegKind_HWRegs | RegKind_COP3 | RegKind_COP0
};
private:
enum KindTy {
k_Immediate, /// An immediate (possibly involving symbol references)
k_Memory, /// Base + Offset Memory Address
k_RegisterIndex, /// A register index in one or more RegKind.
k_Token, /// A simple token
k_RegList, /// A physical register list
} Kind;
public:
MipsOperand(KindTy K, MipsAsmParser &Parser) : Kind(K), AsmParser(Parser) {}
~MipsOperand() override {
switch (Kind) {
case k_Memory:
delete Mem.Base;
break;
case k_RegList:
delete RegList.List;
break;
case k_Immediate:
case k_RegisterIndex:
case k_Token:
break;
}
}
private:
/// For diagnostics, and checking the assembler temporary
MipsAsmParser &AsmParser;
struct Token {
const char *Data;
unsigned Length;
};
struct RegIdxOp {
unsigned Index; /// Index into the register class
RegKind Kind; /// Bitfield of the kinds it could possibly be
struct Token Tok; /// The input token this operand originated from.
const MCRegisterInfo *RegInfo;
};
struct ImmOp {
const MCExpr *Val;
};
struct MemOp {
MipsOperand *Base;
const MCExpr *Off;
};
struct RegListOp {
SmallVector<unsigned, 10> *List;
};
union {
struct Token Tok;
struct RegIdxOp RegIdx;
struct ImmOp Imm;
struct MemOp Mem;
struct RegListOp RegList;
};
SMLoc StartLoc, EndLoc;
/// Internal constructor for register kinds
static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, StringRef Str,
RegKind RegKind,
const MCRegisterInfo *RegInfo,
SMLoc S, SMLoc E,
MipsAsmParser &Parser) {
auto Op = std::make_unique<MipsOperand>(k_RegisterIndex, Parser);
Op->RegIdx.Index = Index;
Op->RegIdx.RegInfo = RegInfo;
Op->RegIdx.Kind = RegKind;
Op->RegIdx.Tok.Data = Str.data();
Op->RegIdx.Tok.Length = Str.size();
Op->StartLoc = S;
Op->EndLoc = E;
return Op;
}
public:
/// Coerce the register to GPR32 and return the real register for the current
/// target.
unsigned getGPR32Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
unsigned ClassID = Mips::GPR32RegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}
/// Coerce the register to GPR32 and return the real register for the current
/// target.
unsigned getGPRMM16Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
unsigned ClassID = Mips::GPR32RegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}
/// Coerce the register to GPR64 and return the real register for the current
/// target.
unsigned getGPR64Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
unsigned ClassID = Mips::GPR64RegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}
private:
/// Coerce the register to AFGR64 and return the real register for the current
/// target.
unsigned getAFGR64Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
if (RegIdx.Index % 2 != 0)
AsmParser.Warning(StartLoc, "Float register should be even.");
return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
.getRegister(RegIdx.Index / 2);
}
/// Coerce the register to FGR64 and return the real register for the current
/// target.
unsigned getFGR64Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
.getRegister(RegIdx.Index);
}
/// Coerce the register to FGR32 and return the real register for the current
/// target.
unsigned getFGR32Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
.getRegister(RegIdx.Index);
}
/// Coerce the register to FCC and return the real register for the current
/// target.
unsigned getFCCReg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
.getRegister(RegIdx.Index);
}
/// Coerce the register to MSA128 and return the real register for the current
/// target.
unsigned getMSA128Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
// It doesn't matter which of the MSA128[BHWD] classes we use. They are all
// identical
unsigned ClassID = Mips::MSA128BRegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}
/// Coerce the register to MSACtrl and return the real register for the
/// current target.
unsigned getMSACtrlReg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
unsigned ClassID = Mips::MSACtrlRegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}
/// Coerce the register to COP0 and return the real register for the
/// current target.
unsigned getCOP0Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!");
unsigned ClassID = Mips::COP0RegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}
/// Coerce the register to COP2 and return the real register for the
/// current target.
unsigned getCOP2Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
unsigned ClassID = Mips::COP2RegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}
/// Coerce the register to COP3 and return the real register for the
/// current target.