Bit-banging synchronous master doesn't reset time registers of its ports

[larry-xmos]

The bit-banging (zero clock-block variant) synchronous master could do with more setup to ensure ports are in a good state to be used for timed outputs.

This can happen if ports have run on different clock blocks prior and now their time registers are out of sync. This happens, for instance if you run an asynchronous master first (two clock blocks) and shut it down using API from pull request #25. As a result, I/O operations block as port timers wrap (typically 0.66ms as 65,536 ticks of 100MHz clock).

The sequence to undo the effect of an asynchronous master is to assign clock block zero to the three key ports, and to reset their time registers by restarting the clock block

     clock cb0 = XS1_CLKBLK_REF;

     set_port_clock(p_sclk, cb0);
     set_port_clock(p_mosi, cb0);
     set_port_clock(p_miso, cb0);

     stop_clock(cb0);
     start_clock(cb0);

This could happen in the synchronous master or, better documented and included in examples

[larry-xmos]

On review I can see that this remains a valid issue. Library code should not rely on clean state of ports and clock blocks.

[larry-xmos]

@ed, @shuchitak – please correct me if I'm wrong that this issue does not apply to XVF3510 where both general-purpose and keyword-related SPI accesses are done through the same synchronous SPI master