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CPU部分大体完成
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-111
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6 files changed

+158
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‎MipsCPU.xise

+14-14
Original file line numberDiff line numberDiff line change
@@ -17,51 +17,51 @@
1717
<files>
1818
<file xil_pn:name="pc_module.v" xil_pn:type="FILE_VERILOG">
1919
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
20-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
20+
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
2121
</file>
2222
<file xil_pn:name="insFetch2insDecode.v" xil_pn:type="FILE_VERILOG">
2323
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
24-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
24+
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
2525
</file>
2626
<file xil_pn:name="regfile.v" xil_pn:type="FILE_VERILOG">
2727
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
28-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
28+
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
2929
</file>
3030
<file xil_pn:name="insDecode.v" xil_pn:type="FILE_VERILOG">
3131
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
32-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
32+
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
3333
</file>
3434
<file xil_pn:name="insDecode2execute.v" xil_pn:type="FILE_VERILOG">
3535
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
36-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
36+
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
3737
</file>
3838
<file xil_pn:name="execute.v" xil_pn:type="FILE_VERILOG">
3939
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
40-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
40+
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
4141
</file>
4242
<file xil_pn:name="execute2memory.v" xil_pn:type="FILE_VERILOG">
4343
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
44-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
44+
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
4545
</file>
4646
<file xil_pn:name="memory.v" xil_pn:type="FILE_VERILOG">
4747
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
48-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
48+
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
4949
</file>
5050
<file xil_pn:name="memory2writeback.v" xil_pn:type="FILE_VERILOG">
5151
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
52-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
52+
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
5353
</file>
5454
<file xil_pn:name="mips.v" xil_pn:type="FILE_VERILOG">
5555
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
56-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
56+
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
5757
</file>
5858
<file xil_pn:name="insRom.v" xil_pn:type="FILE_VERILOG">
5959
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
60-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
60+
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
6161
</file>
6262
<file xil_pn:name="cpu.v" xil_pn:type="FILE_VERILOG">
6363
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
64-
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
64+
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
6565
</file>
6666
<file xil_pn:name="cpu_tb.v" xil_pn:type="FILE_VERILOG">
6767
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
@@ -71,11 +71,11 @@
7171
</file>
7272
<file xil_pn:name="HILO.v" xil_pn:type="FILE_VERILOG">
7373
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
74-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
74+
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
7575
</file>
7676
<file xil_pn:name="ram.v" xil_pn:type="FILE_VERILOG">
7777
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
78-
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
78+
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
7979
</file>
8080
</files>
8181

‎cpu.v

+7-6
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,8 @@
2020
//////////////////////////////////////////////////////////////////////////////////
2121
module cpu(
2222
input rst,
23-
input clk
23+
input clk,
24+
output ram_enabler
2425
);
2526

2627
wire[31:0] instAddr;
@@ -32,19 +33,20 @@ module cpu(
3233
wire[31:0] ram_data_output;
3334
wire[3:0] ram_select_output;
3435
wire ram_write_enabler;
35-
wire ram_enabler;
36+
//wire ram_enabler;
3637

37-
/* mips mips0(
38-
.rst(rst), .clk(clk),
38+
mips mips0(
39+
.rst(rst),
40+
.clk(clk),
3941
.ins_input(inst),
4042
.addr_output(instAddr),
4143
.enabler_output(enabler),
4244

4345
.ram_data(ram_data_input),
4446
.ram_addr_output(ram_addr_output),
45-
.ram_data_output(ram_data_output),
4647
.ram_write_enabler_output(ram_write_enabler),
4748
.ram_select_output(ram_select_output),
49+
.ram_data_output(ram_data_output),
4850
.ram_enabler(ram_enabler)
4951
);
5052

@@ -63,6 +65,5 @@ module cpu(
6365
.data_input(ram_data_output),
6466
.data_output(ram_data_input)
6567
);
66-
*/
6768
endmodule
6869

‎ram.v

+4-4
Original file line numberDiff line numberDiff line change
@@ -28,10 +28,10 @@ module ram(
2828
output reg[31:0] data_output
2929
);
3030

31-
reg[7:0] byte_mem0[0:131071];
32-
reg[7:0] byte_mem1[0:131071];
33-
reg[7:0] byte_mem2[0:131071];
34-
reg[7:0] byte_mem3[0:131071];
31+
reg[7:0] byte_mem0[0:65565];
32+
reg[7:0] byte_mem1[0:65535];
33+
reg[7:0] byte_mem2[0:65535];
34+
reg[7:0] byte_mem3[0:65535];
3535

3636
always @ (posedge clk) begin
3737
if (enabler == 1 && write_enabler == 1) begin

‎transcript

+81-35
Original file line numberDiff line numberDiff line change
@@ -3,148 +3,148 @@
33
# ** Warning: (vlib-34) Library already exists at "work".
44
#
55
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
6-
# Start time: 09:29:22 on Dec 09,2015
6+
# Start time: 10:57:59 on Dec 09,2015
77
# vlog -reportprogress 300 regfile.v
88
# -- Compiling module regfile
99
#
1010
# Top level modules:
1111
# regfile
12-
# End time: 09:29:23 on Dec 09,2015, Elapsed time: 0:00:01
12+
# End time: 10:57:59 on Dec 09,2015, Elapsed time: 0:00:00
1313
# Errors: 0, Warnings: 0
1414
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
15-
# Start time: 09:29:23 on Dec 09,2015
15+
# Start time: 10:57:59 on Dec 09,2015
1616
# vlog -reportprogress 300 pc_module.v
1717
# -- Compiling module pc_module
1818
#
1919
# Top level modules:
2020
# pc_module
21-
# End time: 09:29:23 on Dec 09,2015, Elapsed time: 0:00:00
21+
# End time: 10:57:59 on Dec 09,2015, Elapsed time: 0:00:00
2222
# Errors: 0, Warnings: 0
2323
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
24-
# Start time: 09:29:23 on Dec 09,2015
24+
# Start time: 10:57:59 on Dec 09,2015
2525
# vlog -reportprogress 300 memory2writeback.v
2626
# -- Compiling module memory2writeback
2727
#
2828
# Top level modules:
2929
# memory2writeback
30-
# End time: 09:29:23 on Dec 09,2015, Elapsed time: 0:00:00
30+
# End time: 10:57:59 on Dec 09,2015, Elapsed time: 0:00:00
3131
# Errors: 0, Warnings: 0
3232
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
33-
# Start time: 09:29:23 on Dec 09,2015
33+
# Start time: 10:57:59 on Dec 09,2015
3434
# vlog -reportprogress 300 memory.v
3535
# -- Compiling module memory
3636
#
3737
# Top level modules:
3838
# memory
39-
# End time: 09:29:23 on Dec 09,2015, Elapsed time: 0:00:00
39+
# End time: 10:57:59 on Dec 09,2015, Elapsed time: 0:00:00
4040
# Errors: 0, Warnings: 0
4141
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
42-
# Start time: 09:29:23 on Dec 09,2015
42+
# Start time: 10:57:59 on Dec 09,2015
4343
# vlog -reportprogress 300 insFetch2insDecode.v
4444
# -- Compiling module insFetch2insDecode
4545
#
4646
# Top level modules:
4747
# insFetch2insDecode
48-
# End time: 09:29:23 on Dec 09,2015, Elapsed time: 0:00:00
48+
# End time: 10:57:59 on Dec 09,2015, Elapsed time: 0:00:00
4949
# Errors: 0, Warnings: 0
5050
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
51-
# Start time: 09:29:23 on Dec 09,2015
51+
# Start time: 10:58:00 on Dec 09,2015
5252
# vlog -reportprogress 300 insDecode2execute.v
5353
# -- Compiling module insDecode2execute
5454
#
5555
# Top level modules:
5656
# insDecode2execute
57-
# End time: 09:29:23 on Dec 09,2015, Elapsed time: 0:00:00
57+
# End time: 10:58:00 on Dec 09,2015, Elapsed time: 0:00:00
5858
# Errors: 0, Warnings: 0
5959
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
60-
# Start time: 09:29:24 on Dec 09,2015
60+
# Start time: 10:58:00 on Dec 09,2015
6161
# vlog -reportprogress 300 insDecode.v
6262
# -- Compiling module insDecode
6363
#
6464
# Top level modules:
6565
# insDecode
66-
# End time: 09:29:24 on Dec 09,2015, Elapsed time: 0:00:00
66+
# End time: 10:58:00 on Dec 09,2015, Elapsed time: 0:00:00
6767
# Errors: 0, Warnings: 0
6868
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
69-
# Start time: 09:29:24 on Dec 09,2015
69+
# Start time: 10:58:00 on Dec 09,2015
7070
# vlog -reportprogress 300 HILO.v
7171
# -- Compiling module hilo
7272
#
7373
# Top level modules:
7474
# hilo
75-
# End time: 09:29:24 on Dec 09,2015, Elapsed time: 0:00:00
75+
# End time: 10:58:00 on Dec 09,2015, Elapsed time: 0:00:00
7676
# Errors: 0, Warnings: 0
7777
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
78-
# Start time: 09:29:24 on Dec 09,2015
78+
# Start time: 10:58:00 on Dec 09,2015
7979
# vlog -reportprogress 300 execute2memory.v
8080
# -- Compiling module execute2memory
8181
#
8282
# Top level modules:
8383
# execute2memory
84-
# End time: 09:29:24 on Dec 09,2015, Elapsed time: 0:00:00
84+
# End time: 10:58:00 on Dec 09,2015, Elapsed time: 0:00:00
8585
# Errors: 0, Warnings: 0
8686
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
87-
# Start time: 09:29:24 on Dec 09,2015
87+
# Start time: 10:58:00 on Dec 09,2015
8888
# vlog -reportprogress 300 execute.v
8989
# -- Compiling module execute
9090
#
9191
# Top level modules:
9292
# execute
93-
# End time: 09:29:24 on Dec 09,2015, Elapsed time: 0:00:00
93+
# End time: 10:58:01 on Dec 09,2015, Elapsed time: 0:00:01
9494
# Errors: 0, Warnings: 0
9595
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
96-
# Start time: 09:29:24 on Dec 09,2015
96+
# Start time: 10:58:01 on Dec 09,2015
9797
# vlog -reportprogress 300 ram.v
9898
# -- Compiling module ram
9999
#
100100
# Top level modules:
101101
# ram
102-
# End time: 09:29:24 on Dec 09,2015, Elapsed time: 0:00:00
102+
# End time: 10:58:01 on Dec 09,2015, Elapsed time: 0:00:00
103103
# Errors: 0, Warnings: 0
104104
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
105-
# Start time: 09:29:24 on Dec 09,2015
105+
# Start time: 10:58:01 on Dec 09,2015
106106
# vlog -reportprogress 300 mips.v
107107
# -- Compiling module mips
108108
#
109109
# Top level modules:
110110
# mips
111-
# End time: 09:29:24 on Dec 09,2015, Elapsed time: 0:00:00
111+
# End time: 10:58:01 on Dec 09,2015, Elapsed time: 0:00:00
112112
# Errors: 0, Warnings: 0
113113
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
114-
# Start time: 09:29:24 on Dec 09,2015
114+
# Start time: 10:58:01 on Dec 09,2015
115115
# vlog -reportprogress 300 insRom.v
116116
# -- Compiling module instRom
117117
#
118118
# Top level modules:
119119
# instRom
120-
# End time: 09:29:25 on Dec 09,2015, Elapsed time: 0:00:01
120+
# End time: 10:58:01 on Dec 09,2015, Elapsed time: 0:00:00
121121
# Errors: 0, Warnings: 0
122122
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
123-
# Start time: 09:29:25 on Dec 09,2015
123+
# Start time: 10:58:01 on Dec 09,2015
124124
# vlog -reportprogress 300 cpu.v
125125
# -- Compiling module cpu
126126
#
127127
# Top level modules:
128128
# cpu
129-
# End time: 09:29:25 on Dec 09,2015, Elapsed time: 0:00:00
129+
# End time: 10:58:01 on Dec 09,2015, Elapsed time: 0:00:00
130130
# Errors: 0, Warnings: 0
131131
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
132-
# Start time: 09:29:25 on Dec 09,2015
132+
# Start time: 10:58:02 on Dec 09,2015
133133
# vlog -reportprogress 300 cpu_tb.v
134134
# -- Compiling module cpu_tb
135135
#
136136
# Top level modules:
137137
# cpu_tb
138-
# End time: 09:29:25 on Dec 09,2015, Elapsed time: 0:00:00
138+
# End time: 10:58:02 on Dec 09,2015, Elapsed time: 0:00:00
139139
# Errors: 0, Warnings: 0
140140
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
141-
# Start time: 09:29:25 on Dec 09,2015
141+
# Start time: 10:58:02 on Dec 09,2015
142142
# vlog -reportprogress 300 d:/Xilinx/14.7/ISE_DS/ISE/verilog/src/glbl.v
143143
# -- Compiling module glbl
144144
#
145145
# Top level modules:
146146
# glbl
147-
# End time: 09:29:25 on Dec 09,2015, Elapsed time: 0:00:00
147+
# End time: 10:58:02 on Dec 09,2015, Elapsed time: 0:00:00
148148
# Errors: 0, Warnings: 0
149149
# // ModelSim PE Student Edition 10.4a Apr 7 2015
150150
# //
@@ -165,7 +165,7 @@
165165
# // FOR HIGHER EDUCATION PURPOSES ONLY
166166
# //
167167
# vsim -gui -do "do {cpu_tb.fdo}"
168-
# Start time: 09:29:25 on Dec 09,2015
168+
# Start time: 10:58:02 on Dec 09,2015
169169
# Loading work.cpu_tb
170170
# Loading work.cpu
171171
# Loading work.mips
@@ -182,8 +182,54 @@
182182
# Loading work.instRom
183183
# Loading work.ram
184184
# Loading work.glbl
185+
# ** Warning: (vsim-3017) cpu_tb.v(32): [TFMPC] - Too few port connections. Expected 3, found 2.
186+
# Time: 0 ps Iteration: 0 Instance: /cpu_tb/uut File: cpu.v
187+
# ** Warning: (vsim-3722) cpu_tb.v(32): [TFMPC] - Missing connection for port 'ram_enabler'.
185188
# .main_pane.wave.interior.cs.body.pw.wf
186189
# .main_pane.structure.interior.cs.body.struct
187190
# .main_pane.objects.interior.cs.body.tree
188-
# End time: 09:31:06 on Dec 09,2015, Elapsed time: 0:01:41
189-
# Errors: 0, Warnings: 0
191+
add wave -position end sim:/cpu_tb/uut/mips0/regfile0/regs[1]
192+
add wave -position end sim:/cpu_tb/uut/mips0/regfile0/regs[2]
193+
add wave -position end sim:/cpu_tb/uut/mips0/regfile0/regs[3]
194+
add wave -position end sim:/cpu_tb/uut/mips0/regfile0/regs[4]
195+
restart -f
196+
# ** Warning: (vsim-3017) cpu_tb.v(32): [TFMPC] - Too few port connections. Expected 3, found 2.
197+
# Time: 0 ps Iteration: 0 Instance: /cpu_tb/uut File: cpu.v
198+
# ** Warning: (vsim-3722) cpu_tb.v(32): [TFMPC] - Missing connection for port 'ram_enabler'.
199+
run -all
200+
# ** Note: $stop : cpu_tb.v(48)
201+
# Time: 100195 ns Iteration: 0 Instance: /cpu_tb
202+
# Break in Module cpu_tb at cpu_tb.v line 48
203+
# Error opening E:/HDL/MipsCPU/(vsim-3017) cpu_tb.v
204+
# Path name 'E:/HDL/MipsCPU/(vsim-3017) cpu_tb.v' doesn't exist.
205+
restart -f
206+
# ** Warning: (vsim-3017) cpu_tb.v(32): [TFMPC] - Too few port connections. Expected 3, found 2.
207+
# Time: 0 ps Iteration: 0 Instance: /cpu_tb/uut File: cpu.v
208+
# ** Warning: (vsim-3722) cpu_tb.v(32): [TFMPC] - Missing connection for port 'ram_enabler'.
209+
run -all
210+
# ** Note: $stop : cpu_tb.v(48)
211+
# Time: 100195 ns Iteration: 0 Instance: /cpu_tb
212+
# Break in Module cpu_tb at cpu_tb.v line 48
213+
restartt -f
214+
# invalid command name "restartt"
215+
restart -f
216+
# ** Warning: (vsim-3017) cpu_tb.v(32): [TFMPC] - Too few port connections. Expected 3, found 2.
217+
# Time: 0 ps Iteration: 0 Instance: /cpu_tb/uut File: cpu.v
218+
# ** Warning: (vsim-3722) cpu_tb.v(32): [TFMPC] - Missing connection for port 'ram_enabler'.
219+
run -all
220+
# ** Note: $stop : cpu_tb.v(48)
221+
# Time: 100195 ns Iteration: 0 Instance: /cpu_tb
222+
# Break in Module cpu_tb at cpu_tb.v line 48
223+
restart -f
224+
# ** Warning: (vsim-3017) cpu_tb.v(32): [TFMPC] - Too few port connections. Expected 3, found 2.
225+
# Time: 0 ps Iteration: 0 Instance: /cpu_tb/uut File: cpu.v
226+
# ** Warning: (vsim-3722) cpu_tb.v(32): [TFMPC] - Missing connection for port 'ram_enabler'.
227+
run -all
228+
# ** Note: $stop : cpu_tb.v(48)
229+
# Time: 100195 ns Iteration: 0 Instance: /cpu_tb
230+
# Break in Module cpu_tb at cpu_tb.v line 48
231+
add wave -position end sim:/cpu_tb/uut/mips0/regfile0/regs[29]
232+
add wave -position end sim:/cpu_tb/uut/mips0/regfile0/regs[30]
233+
add wave -position end sim:/cpu_tb/uut/mips0/regfile0/regs[31]
234+
# End time: 11:12:27 on Dec 09,2015, Elapsed time: 0:14:25
235+
# Errors: 2, Warnings: 10

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