-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathradixtest.v
executable file
·124 lines (95 loc) · 1.56 KB
/
radixtest.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:09:44 08/14/2016
// Design Name: radix4booth
// Module Name: G:/karma/radix4/radixtest.v
// Project Name: radix4
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: radix4booth
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module radixtest;
// Inputs
reg [7:0] sw;
reg go;
reg clk;
reg rst;
// Outputs
wire [15:0] display;
wire [2:0] state;
// Instantiate the Unit Under Test (UUT)
radix4booth uut (
.sw(sw),
.go(go),
.clk(clk),
.rst(rst),
.display(display),
.state(state)
);
always #10 clk = ~clk;
initial begin
// Initialize Inputs
sw = 68;
go = 1;
clk = 1;
rst = 1;
#10;
sw =68;
go = 1;
rst = 1;
#10;
sw = 68;
go = 1;
rst = 0;
#10;
sw = 68;
go = 1;
rst = 0;
#10;
sw = 68;
go = 1;
rst = 0;
#10;
sw = 68;
go = 1;
rst = 0;
#10;
sw = 68;
go = 1;
rst = 0;
#10;
sw = 68;
go = 1;
rst = 0;
#10;
sw =68;
go = 0;
rst = 0;
#10;
sw = 35;
go = 0;
rst = 0;
#10;
sw = 35;
go = 1;
rst = 0;
#10;
sw = 35;
go = 1;
rst = 0;
#10;
// Add stimulus here
end
endmodule