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Hi, great project! Please consider supporting Symbolator for generating hardware description language blocks like vhdl or verilog.
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Interesting project! https://github.com/kevinpt/symbolator
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Since Symbolator seems unmaintained (for a long time) maybe https://github.com/nturley/netlistsvg could convert VDHL and/or Verilog files as images?
Another alternative: https://github.com/circuitikz/circuitikz
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Hi, great project!
Please consider supporting Symbolator for generating hardware description language blocks like vhdl or verilog.
The text was updated successfully, but these errors were encountered: