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Array literals flow into Verilog unchanged #260

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YikeZhou opened this issue Nov 2, 2023 · 0 comments

YikeZhou commented Nov 2, 2023 •

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Edit: Could it be because the feature is not synthesizable (all the time)? Apologize if this is a "won't fix".

Input:

module top(output logic[7:0] o);
   assign o = '{0:1, 3:1, 7:1, default:0};
endmodule

Output:

module top (o);
        output wire [7:0] o;
        assign o = '{
                0: 1,
                3: 1,
                7: 1,
                default: 0
        };
endmodule

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