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Bug #3

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ShevtsovNikita opened this issue Mar 21, 2023 · 1 comment
Open

Bug #3

ShevtsovNikita opened this issue Mar 21, 2023 · 1 comment

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@ShevtsovNikita
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I found a bug when executing two commands MULH and MUL one after the other

This is correct result achieved by executing solo MULH operation:
image

This is correct result achieved by executing solo MUL operation:
image

And this is incorrect result when MUL goes after MULH:
image

It happens because control signal "is_mulh" and result of multiplication "mul_rd" performed in combinational logic.
image

So in 1st clock "is_mulh" already takes the value of MUL and "result" takes the value of lower part of "rd" when it have to keep value of high part
image

@jg-fossh
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jg-fossh commented Aug 7, 2024

The design seems to expect that signals will be held stable for at least a couple of clocks. Maybe that is expected behavior of the SERV core. @ShevtsovNikita do you have still have your testbench by any chance? I forked the project and made a quick update in a branch, but I haven't tested it. MDU Product & Handshake Alignment.

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