dts: n6: Allow using axisram2 in chainloaded application

Make axisram2 which is used in fsbl mode available as well to
chainloaded application in order not to loose 1M of RAM

In order to avoid conflicts with bootloader, verify that code + ro data
of the loaded application won't go further than bootloader start address.
This is done with a linker assert.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>

Author: erwango

dts/arm/st/n6/stm32n657X0.dtsi

@@ -8,11 +8,13 @@
 
 / {
 	axisram1: memory@34000000 {
-		/* 400 kB of FLEXRAM followed by 624 kB of AXISRAM1 */
-		reg = <0x34000000 (DT_SIZE_K(400) + DT_SIZE_K(624))>;
+		/* This section is the RAM available to the chainloaded application */
+		/* 400 kB of FLEXRAM followed by 624 kB of AXISRAM1 + AXISRAM2 */
+		reg = <0x34000000 (DT_SIZE_K(400) + DT_SIZE_K(624) + DT_SIZE_M(1))>;
 	};
 
 	axisram2: memory@34180400 {
+		/* This section is the RAM available to FSBL application */
 		reg = <0x34180400 DT_SIZE_K(511)>;
 	};
 };

soc/st/stm32/stm32n6x/CMakeLists.txt

@@ -9,6 +9,8 @@ zephyr_include_directories(.)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
 
+zephyr_linker_sources_ifdef(CONFIG_BOOTLOADER_MCUBOOT SECTIONS ram_check.ld)
+
 if(NOT CONFIG_BOOTLOADER_MCUBOOT)
 
   if(${CMAKE_HOST_SYSTEM_NAME} STREQUAL Windows)

soc/st/stm32/stm32n6x/ram_check.ld

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/linker/linker-defs.h>
+
+#define MCUBOOT_START_ADDR DT_PROP_BY_IDX(DT_NODELABEL(axisram2), reg, 0)
+
+ASSERT((__kernel_ram_start < (MCUBOOT_START_ADDR - CONFIG_ROM_START_OFFSET)),
+       "
+       Image is too large to fit RAMLOAD configuration. Consider using XIP.
+       ")