@@ -322,26 +322,26 @@ int EWLmemcmp(const void *s1, const void *s2, uint32_t n)
322322 return memcmp (s1 , s2 , n );
323323}
324324
325- i32 EWLWaitHwRdy (const void * instance , uint32_t * slicesReady )
325+ i32 EWLWaitHwRdy (const void * instance , uint32_t * slices_ready )
326326{
327327 struct stm32_venc_ewl * inst = (struct stm32_venc_ewl * )instance ;
328328 const struct stm32_venc_config * config = inst -> config ;
329329 int32_t ret = EWL_HW_WAIT_TIMEOUT ;
330330 volatile uint32_t irq_stats ;
331- uint32_t prevSlicesReady = 0 ;
331+ uint32_t prev_slices_ready = 0 ;
332332 k_timepoint_t timeout = sys_timepoint_calc (K_MSEC (EWL_TIMEOUT ));
333333 uint32_t start = sys_clock_tick_get_32 ();
334334
335335 __ASSERT_NO_MSG (inst != NULL );
336336
337337 /* check how to clear IRQ flags for VENC */
338- uint32_t clrByWrite1 = EWLReadReg (inst , BASE_HWFuse2 ) & HWCFGIrqClearSupport ;
338+ uint32_t clr_by_write_1 = EWLReadReg (inst , BASE_HWFuse2 ) & HWCFGIrqClearSupport ;
339339
340340 do {
341341 irq_stats = sys_read32 (config -> reg + BASE_HEncIRQ );
342342 /* get the number of completed slices from ASIC registers. */
343- if (slicesReady != NULL && * slicesReady > prevSlicesReady ) {
344- * slicesReady = FIELD_GET (NUM_SLICES_READY_MASK ,
343+ if (slices_ready != NULL && * slices_ready > prev_slices_ready ) {
344+ * slices_ready = FIELD_GET (NUM_SLICES_READY_MASK ,
345345 sys_read32 (config -> reg + BASE_HEncControl7 ));
346346 }
347347
@@ -362,7 +362,7 @@ i32 EWLWaitHwRdy(const void *instance, uint32_t *slicesReady)
362362
363363 irq_stats &= ~(ASIC_STATUS_SLICE_READY | ASIC_IRQ_LINE );
364364
365- if (clrByWrite1 != 0UL ) {
365+ if (clr_by_write_1 != 0UL ) {
366366 clr_stats = ASIC_STATUS_SLICE_READY | ASIC_IRQ_LINE ;
367367 } else {
368368 clr_stats = irq_stats ;
@@ -373,7 +373,7 @@ i32 EWLWaitHwRdy(const void *instance, uint32_t *slicesReady)
373373 break ;
374374 }
375375
376- if (slicesReady != NULL && * slicesReady > prevSlicesReady ) {
376+ if (slices_ready != NULL && * slices_ready > prev_slices_ready ) {
377377 ret = EWL_OK ;
378378 break ;
379379 }
@@ -387,8 +387,8 @@ i32 EWLWaitHwRdy(const void *instance, uint32_t *slicesReady)
387387
388388 LOG_DBG ("encoding = %d ms" , k_ticks_to_ms_ceil32 (sys_clock_tick_get_32 () - start ));
389389
390- if (slicesReady != NULL ) {
391- LOG_DBG ("slicesReady = %d" , * slicesReady );
390+ if (slices_ready != NULL ) {
391+ LOG_DBG ("slices_ready = %d" , * slices_ready );
392392 }
393393
394394 return EWL_OK ;
@@ -554,21 +554,21 @@ static int encoder_prepare(struct stm32_venc_data *data)
554554static int encoder_start (struct stm32_venc_data * data , struct video_buffer * output )
555555{
556556 H264EncRet h264ret ;
557- H264EncIn encIn = {0 };
558- H264EncOut encOut = {0 };
557+ H264EncIn enc_in = {0 };
558+ H264EncOut enc_out = {0 };
559559
560- encIn .pOutBuf = (uint32_t * )output -> buffer ;
561- encIn .busOutBuf = (uint32_t )encIn .pOutBuf ;
562- encIn .outBufSize = output -> size ;
560+ enc_in .pOutBuf = (uint32_t * )output -> buffer ;
561+ enc_in .busOutBuf = (uint32_t )enc_in .pOutBuf ;
562+ enc_in .outBufSize = output -> size ;
563563
564564 /* create stream */
565- h264ret = H264EncStrmStart (data -> encoder , & encIn , & encOut );
565+ h264ret = H264EncStrmStart (data -> encoder , & enc_in , & enc_out );
566566 if (h264ret != H264ENC_OK ) {
567567 LOG_ERR ("H264EncStrmStart error=%d" , h264ret );
568568 return - EIO ;
569569 }
570570
571- output -> bytesused = encOut .streamSize ;
571+ output -> bytesused = enc_out .streamSize ;
572572 LOG_DBG ("SPS/PPS generated, size= %d" , output -> bytesused );
573573
574574 data -> resync = true;
@@ -578,11 +578,11 @@ static int encoder_start(struct stm32_venc_data *data, struct video_buffer *outp
578578
579579static int encoder_end (struct stm32_venc_data * data )
580580{
581- H264EncIn encIn = {0 };
582- H264EncOut encOut = {0 };
581+ H264EncIn enc_in = {0 };
582+ H264EncOut enc_out = {0 };
583583
584584 if (data -> encoder != NULL ) {
585- H264EncStrmEnd (data -> encoder , & encIn , & encOut );
585+ H264EncStrmEnd (data -> encoder , & enc_in , & enc_out );
586586 data -> encoder = NULL ;
587587 }
588588
@@ -595,8 +595,8 @@ static int encode_frame(struct stm32_venc_data *data)
595595 H264EncRet h264ret = H264ENC_FRAME_READY ;
596596 struct video_buffer * input ;
597597 struct video_buffer * output ;
598- H264EncIn encIn = {0 };
599- H264EncOut encOut = {0 };
598+ H264EncIn enc_in = {0 };
599+ H264EncOut enc_out = {0 };
600600
601601 if (k_fifo_is_empty (& data -> in_fifo_in ) || k_fifo_is_empty (& data -> out_fifo_in )) {
602602 /* Encoding deferred to next buffer queueing */
@@ -624,38 +624,38 @@ static int encode_frame(struct stm32_venc_data *data)
624624 /* one key frame every seconds */
625625 if ((data -> frame_nb % VENC_DEFAULT_FRAMERATE ) == 0 || data -> resync ) {
626626 /* if frame is the first or resync needed: set as intra coded */
627- encIn .codingType = H264ENC_INTRA_FRAME ;
627+ enc_in .codingType = H264ENC_INTRA_FRAME ;
628628 } else {
629629 /* if there was a frame previously, set as predicted */
630- encIn .timeIncrement = 1 ;
631- encIn .codingType = H264ENC_PREDICTED_FRAME ;
630+ enc_in .timeIncrement = 1 ;
631+ enc_in .codingType = H264ENC_PREDICTED_FRAME ;
632632 }
633633
634- encIn .ipf = H264ENC_REFERENCE_AND_REFRESH ;
635- encIn .ltrf = H264ENC_REFERENCE ;
634+ enc_in .ipf = H264ENC_REFERENCE_AND_REFRESH ;
635+ enc_in .ltrf = H264ENC_REFERENCE ;
636636
637637 /* set input buffers to structures */
638- encIn .busLuma = (ptr_t )input -> buffer ;
639- encIn .busChromaU = (ptr_t )encIn .busLuma + data -> in_fmt .width * data -> in_fmt .height ;
638+ enc_in .busLuma = (ptr_t )input -> buffer ;
639+ enc_in .busChromaU = (ptr_t )enc_in .busLuma + data -> in_fmt .width * data -> in_fmt .height ;
640640
641- encIn .pOutBuf = (uint32_t * )output -> buffer ;
642- encIn .busOutBuf = (uint32_t )encIn .pOutBuf ;
643- encIn .outBufSize = output -> size ;
644- encOut .streamSize = 0 ;
641+ enc_in .pOutBuf = (uint32_t * )output -> buffer ;
642+ enc_in .busOutBuf = (uint32_t )enc_in .pOutBuf ;
643+ enc_in .outBufSize = output -> size ;
644+ enc_out .streamSize = 0 ;
645645
646- h264ret = H264EncStrmEncode (data -> encoder , & encIn , & encOut , NULL , NULL , NULL );
647- output -> bytesused = encOut .streamSize ;
648- LOG_DBG ("output=%p, encOut .streamSize=%d" , output , encOut .streamSize );
646+ h264ret = H264EncStrmEncode (data -> encoder , & enc_in , & enc_out , NULL , NULL , NULL );
647+ output -> bytesused = enc_out .streamSize ;
648+ LOG_DBG ("output=%p, enc_out .streamSize=%d" , output , enc_out .streamSize );
649649
650650 switch (h264ret ) {
651651 case H264ENC_FRAME_READY :
652652 /* save stream */
653- if (encOut .streamSize == 0 ) {
653+ if (enc_out .streamSize == 0 ) {
654654 /* Nothing encoded */
655655 data -> resync = true;
656656 goto out ;
657657 }
658- output -> bytesused = encOut .streamSize ;
658+ output -> bytesused = enc_out .streamSize ;
659659 break ;
660660 case H264ENC_FUSE_ERROR :
661661 LOG_ERR ("H264EncStrmEncode error=%d" , h264ret );
@@ -841,19 +841,19 @@ static const struct stm32_venc_config stm32_venc_config_0 = {
841841 .irq_config = stm32_venc_irq_config_func ,
842842};
843843
844- static void RISAF_Config (void )
844+ static void risaf_config (void )
845845{
846846 /* Define and initialize the master configuration structure */
847- RIMC_MasterConfig_t RIMC_master = {0 };
847+ RIMC_MasterConfig_t rimc_master = {0 };
848848
849849 /* Enable the clock for the RIFSC (RIF Security Controller) */
850850 __HAL_RCC_RIFSC_CLK_ENABLE ();
851851
852- RIMC_master .MasterCID = RIF_CID_1 ;
853- RIMC_master .SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV ;
852+ rimc_master .MasterCID = RIF_CID_1 ;
853+ rimc_master .SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV ;
854854
855855 /* Configure the master attributes for the video encoder peripheral (VENC) */
856- HAL_RIF_RIMC_ConfigMasterAttributes (RIF_MASTER_INDEX_VENC , & RIMC_master );
856+ HAL_RIF_RIMC_ConfigMasterAttributes (RIF_MASTER_INDEX_VENC , & rimc_master );
857857
858858 /* Set the secure and privileged attributes for the VENC as a slave */
859859 HAL_RIF_RISC_SetSlaveSecureAttributes (RIF_RISC_PERIPH_INDEX_VENC ,
@@ -890,7 +890,7 @@ static int stm32_venc_init(const struct device *dev)
890890 /* Run IRQ init */
891891 config -> irq_config (dev );
892892
893- RISAF_Config ();
893+ risaf_config ();
894894
895895 LOG_DBG ("CPU frequency : %d" , HAL_RCC_GetCpuClockFreq () / 1000000 );
896896 LOG_DBG ("sysclk frequency : %d" , HAL_RCC_GetSysClockFreq () / 1000000 );
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