dts: bindings: clock: stm32wba pll clock add div-p

Add missing div-p division factor for pll clock and
respective tests in test/clock_control/stm32_clock_configuration

Signed-off-by: Mario Paja <mariopaja@hotmail.com>

Author: mariopaja

dts/bindings/clock/st,stm32wba-pll-clock.yaml

@@ -51,6 +51,13 @@ properties:
         PLLx multiplication factor for VCO
         Valid range: 4 - 512
 
+  div-p:
+    type: int
+    required: true
+    description: |
+        PLLx DIVP division factor
+        Valid range: 1 - 128
+
   div-q:
     type: int
     description: |

tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/clear_clocks.overlay

@@ -21,6 +21,7 @@
 &pll1 {
 	/delete-property/ div-m;
 	/delete-property/ mul-n;
+	/delete-property/ div-p;
 	/delete-property/ div-q;
 	/delete-property/ div-r;
 	/delete-property/ clocks;

tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100.overlay

@@ -17,6 +17,7 @@
 &pll1 {
 	div-m = <8>;
 	mul-n = <100>;
+	div-p = <2>;
 	div-q = <2>;
 	div-r = <4>;
 	clocks = <&clk_hse>;

tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100_ahb_50.overlay

@@ -17,6 +17,7 @@
 &pll1 {
 	div-m = <8>;
 	mul-n = <100>;
+	div-p = <2>;
 	div-q = <2>;
 	div-r = <4>;
 	clocks = <&clk_hse>;