boards: arm: fix generation of DDR4 memory section

wearyzen · wearyzen · commit 5e7bd25cdde7 · 2025-08-27T10:14:23.000+01:00
What is the change? Split and redefine the DDR4 device tree nodes, in their respective board variants so that linker scripts automatically generates a memory section for each node. Why do we need this change? According to the official memory map of Corstone-320 available here: https://developer.arm.com/documentation/109760/0000/SSE-320-FVP/SSE-320-FVP-memory-map the non-secure world alias of DDR4 starts at 0x6000_0000 and the secure world alias starts at 0x7000_0000. Previously, the shared DDR4 node in mps4_common.dtsi listed multiple regions, but Zephyr generated a linker memory region **only** for the first address (0x6000_0000). This broke samples like `tflm_ethosu`, on Corstone-320, which expect DDR4 memory region to start at 0x7000_0000 for secure variants of the MPS4 board. Moving DDR4 definitions to per-board dts files ensures Zephyr creates correct memory regions for each variant. This also makes all the DDR4 regions available for applications to use not just the first (applications would otherwise have to use some linker magic to make those regions available in linker script). Signed-off-by: Sudan Landge <sudan.landge@arm.com>
diff --git a/boards/arm/mps4/mps4_common.dtsi b/boards/arm/mps4/mps4_common.dtsi
@@ -97,21 +97,6 @@
 		zephyr,memory-region = "NULL_PTR_DETECT";
 		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_FLASH) )>;
 	};
-
-	/* DDR4 - 2G, alternates non-secure/secure every 256M */
-	ddr4: memory@60000000 {
-		device_type = "memory";
-		compatible = "zephyr,memory-region";
-		reg = <0x60000000 DT_SIZE_M(256)
-		       0x70000000 DT_SIZE_M(256)
-		       0x80000000 DT_SIZE_M(256)
-		       0x90000000 DT_SIZE_M(256)
-		       0xa0000000 DT_SIZE_M(256)
-		       0xb0000000 DT_SIZE_M(256)
-		       0xc0000000 DT_SIZE_M(256)
-		       0xd0000000 DT_SIZE_M(256)>;
-		zephyr,memory-region = "DDR4";
-	};
 };
 
 &nvic {
diff --git a/boards/arm/mps4/mps4_corstone315_fvp.dts b/boards/arm/mps4/mps4_corstone315_fvp.dts
@@ -83,6 +83,59 @@
 		zephyr,memory-region = "ISRAM";
 	};
 
+	/* The DDR4 node and zephyr,memory-region follow the naming convention
+	 * ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
+	 * which is named as "DDR4" to be compatible with existing
+	 * samples/tests that expect DDR4 node and region to be of the same name.
+	 */
+	ddr4_6_ns: memory@60000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_6_NS";
+	};
+
+	ddr4: memory@70000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x70000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4";
+	};
+
+	ddr4_8_ns: memory@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_8_NS";
+	};
+
+	ddr4_9_s: memory@90000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x90000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_9_S";
+	};
+
+	ddr4_a_ns: memory@a0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xa0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_A_NS";
+	};
+
+	ddr4_b_s: memory@b0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xb0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_B_S";
+	};
+
+	ddr4_c_ns: memory@c0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xc0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_C_NS";
+	};
+
+	ddr4_d_s: memory@d0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xd0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_D_S";
+	};
+
 	soc {
 		peripheral@50000000 {
 			#address-cells = <1>;
diff --git a/boards/arm/mps4/mps4_corstone315_fvp_ns.dts b/boards/arm/mps4/mps4_corstone315_fvp_ns.dts
@@ -68,6 +68,35 @@
 		zephyr,memory-region = "ISRAM";
 	};
 
+	/* The DDR4 node and zephyr,memory-region follow the naming convention
+	 * ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
+	 * which is named as "DDR4" to be compatible with existing
+	 * samples/tests that expect DDR4 node and region to be of the same name.
+	 */
+	ddr4: memory@60000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4";
+	};
+
+	ddr4_8_ns: memory@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_8_NS";
+	};
+
+	ddr4_a_ns: memory@a0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xa0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_A_NS";
+	};
+
+	ddr4_c_ns: memory@c0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xc0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_C_NS";
+	};
+
 	reserved-memory {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/boards/arm/mps4/mps4_corstone320_fvp.dts b/boards/arm/mps4/mps4_corstone320_fvp.dts
@@ -83,6 +83,59 @@
 		zephyr,memory-region = "ISRAM";
 	};
 
+	/* The DDR4 node and zephyr,memory-region follow the naming convention
+	 * ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
+	 * which is named as "DDR4" to be compatible with existing
+	 * samples/tests that expect DDR4 node and region to be of the same name.
+	 */
+	ddr4_6_ns: memory@60000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_6_NS";
+	};
+
+	ddr4: memory@70000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x70000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4";
+	};
+
+	ddr4_8_ns: memory@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_8_NS";
+	};
+
+	ddr4_9_s: memory@90000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x90000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_9_S";
+	};
+
+	ddr4_a_ns: memory@a0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xa0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_A_NS";
+	};
+
+	ddr4_b_s: memory@b0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xb0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_B_S";
+	};
+
+	ddr4_c_ns: memory@c0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xc0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_C_NS";
+	};
+
+	ddr4_d_s: memory@d0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xd0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_D_S";
+	};
+
 	soc {
 		peripheral@50000000 {
 			#address-cells = <1>;
diff --git a/boards/arm/mps4/mps4_corstone320_fvp_ns.dts b/boards/arm/mps4/mps4_corstone320_fvp_ns.dts
@@ -68,6 +68,35 @@
 		zephyr,memory-region = "ISRAM";
 	};
 
+	/* The DDR4 node and zephyr,memory-region follow the naming convention
+	 * ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
+	 * which is named as "DDR4" to be compatible with existing
+	 * samples/tests that expect DDR4 node and region to be of the same name.
+	 */
+	ddr4: memory@60000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4";
+	};
+
+	ddr4_8_ns: memory@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_8_NS";
+	};
+
+	ddr4_a_ns: memory@a0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xa0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_A_NS";
+	};
+
+	ddr4_c_ns: memory@c0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xc0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_C_NS";
+	};
+
 	reserved-memory {
 		#address-cells = <1>;
 		#size-cells = <1>;
