Skip to content

Commit a80dd6a

Browse files
author
Yurii Hamann
committed
arch: arm: stm32: Basic STM32F7 family support
Includes support for STM32F746xG subfamily Related to the issue #6981 Signed-off-by: Yurii Hamann <yurii@hamann.site>
1 parent 1432a83 commit a80dd6a

File tree

14 files changed

+610
-0
lines changed

14 files changed

+610
-0
lines changed

‎arch/arm/soc/st_stm32/stm32f7/CMakeLists.txt‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
zephyr_include_directories(${ZEPHYR_BASE}/drivers)
2+
zephyr_sources(
3+
soc.c
4+
)
5+
zephyr_sources_ifdef(CONFIG_GPIO soc_gpio.c)

‎arch/arm/soc/st_stm32/stm32f7/Kconfig.defconfig.series‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
# Kconfig.defconfig.series - ST Microelectronics STM32F7 MCU line
2+
#
3+
# Copyright (c) 2018 Yurii Hamann
4+
#
5+
# SPDX-License-Identifier: Apache-2.0
6+
#
7+
8+
if SOC_SERIES_STM32F7X
9+
10+
source "arch/arm/soc/st_stm32/stm32f7/Kconfig.defconfig.stm32f7*"
11+
12+
config SOC_SERIES
13+
default stm32f7
14+
15+
endif # SOC_SERIES_STM32F7X

‎arch/arm/soc/st_stm32/stm32f7/Kconfig.defconfig.stm32f746xg‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
# Kconfig - ST STM32F746XG MCU configuration options
2+
#
3+
# Copyright (c) 2018 Yurii Hamann
4+
#
5+
# SPDX-License-Identifier: Apache-2.0
6+
#
7+
8+
if SOC_STM32F746XG
9+
10+
config SOC
11+
string
12+
default stm32f746xx
13+
14+
config NUM_IRQS
15+
int
16+
default 97
17+
18+
endif # SOC_STM32F746XG

‎arch/arm/soc/st_stm32/stm32f7/Kconfig.series‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
# Kconfig - ST Microelectronics STM32F7 MCU series
2+
#
3+
# Copyright (c) 2018 Yurii Hamann
4+
#
5+
# SPDX-License-Identifier: Apache-2.0
6+
#
7+
8+
config SOC_SERIES_STM32F7X
9+
bool "STM32F7x Series MCU"
10+
select CPU_CORTEX_M7
11+
select CPU_HAS_FPU
12+
select SOC_FAMILY_STM32
13+
select SYS_POWER_LOW_POWER_STATE_SUPPORTED
14+
select HAS_STM32CUBE
15+
select CPU_HAS_MPU
16+
select CPU_HAS_SYSTICK
17+
select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
18+
help
19+
Enable support for STM32F7 MCU series

‎arch/arm/soc/st_stm32/stm32f7/Kconfig.soc‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
# Kconfig.soc - ST Microelectronics STM32F7 MCU line
2+
#
3+
# Copyright (c) 2018 Yurii Hamann
4+
#
5+
# SPDX-License-Identifier: Apache-2.0
6+
#
7+
8+
choice
9+
prompt "STM32F7x MCU Selection"
10+
depends on SOC_SERIES_STM32F7X
11+
12+
config SOC_STM32F746XG
13+
bool "STM32F746XG"
14+
15+
endchoice
16+
17+
18+
choice
19+
prompt "Configure Bootloader Options"
20+
depends on MPU_ENABLE
21+
22+
config BL_BOOTLOADER
23+
bool "Build the Bootloader"
24+
25+
config BL_APPLICATION
26+
bool "Build an Application"
27+
28+
endchoice

‎arch/arm/soc/st_stm32/stm32f7/dts.fixup‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
/* SoC level DTS fixup file */
2+
3+
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
4+
5+
#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40011000_BASE_ADDRESS
6+
#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40011000_CURRENT_SPEED
7+
#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40011000_IRQ_0_PRIORITY
8+
#define CONFIG_UART_STM32_PORT_1_NAME ST_STM32_USART_40011000_LABEL
9+
#define PORT_1_IRQ ST_STM32_USART_40011000_IRQ_0
10+
11+
#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS
12+
#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED
13+
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
14+
#define CONFIG_UART_STM32_PORT_2_NAME ST_STM32_USART_40004400_LABEL
15+
#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0
16+
17+
#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS
18+
#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_CURRENT_SPEED
19+
#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY
20+
#define CONFIG_UART_STM32_PORT_3_NAME ST_STM32_USART_40004800_LABEL
21+
#define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0
22+
23+
#define CONFIG_UART_STM32_PORT_6_NAME ST_STM32_USART_40011400_LABEL
24+
#define CONFIG_UART_STM32_PORT_6_BASE_ADDRESS ST_STM32_USART_40011400_BASE_ADDRESS
25+
#define CONFIG_UART_STM32_PORT_6_BAUD_RATE ST_STM32_USART_40011400_CURRENT_SPEED
26+
#define CONFIG_UART_STM32_PORT_6_IRQ_PRI ST_STM32_USART_40011400_IRQ_0_PRIORITY
27+
#define PORT_6_IRQ ST_STM32_USART_40011400_IRQ_0
28+
29+
/* End of SoC Level DTS fixup file */

‎arch/arm/soc/st_stm32/stm32f7/flash_registers.h‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
/*
2+
* Copyright (c) 2018 Yurii Hamann
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#ifndef _STM32F7X_FLASH_REGISTERS_H_
8+
#define _STM32F7X_FLASH_REGISTERS_H_
9+
10+
/**
11+
* @brief
12+
*
13+
* Based on reference manual:
14+
*
15+
* Chapter 3.4: Embedded Flash Memory
16+
*/
17+
18+
union __flash_acr {
19+
u32_t val;
20+
struct {
21+
u32_t latency :4 __packed;
22+
u32_t rsvd__4_7 :4 __packed;
23+
u32_t prften :1 __packed;
24+
u32_t icen :1 __packed;
25+
u32_t dcen :1 __packed;
26+
u32_t icrst :1 __packed;
27+
u32_t dcrst :1 __packed;
28+
u32_t rsvd__13_31 :19 __packed;
29+
} bit;
30+
};
31+
32+
/* 3.8.7 Embedded flash registers */
33+
struct stm32f7x_flash {
34+
volatile union __flash_acr acr;
35+
volatile u32_t keyr;
36+
volatile u32_t optkeyr;
37+
volatile u32_t sr;
38+
volatile u32_t cr;
39+
volatile u32_t optcr;
40+
};
41+
42+
#endif /* _STM32F7X_FLASHREGISTERS_H_ */

‎arch/arm/soc/st_stm32/stm32f7/gpio_registers.h‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
/*
2+
* Copyright (c) 2018 Yurii Hamann
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#ifndef _STM32F7X_GPIO_REGISTERS_H_
8+
#define _STM32F7X_GPIO_REGISTERS_H_
9+
10+
/**
11+
* @brief Driver for GPIO of STM32F7X family processor.
12+
*
13+
* Based on reference manual:
14+
* RM0385 Reference manual STM32F75xxx and STM32F74xxx
15+
* advanced ARM(r)-based 32-bit MCUs
16+
*
17+
* Chapter 6: General-purpose I/Os (GPIOs)
18+
*/
19+
20+
/* 6.4 GPIO registers - each GPIO port controls 16 pins */
21+
struct stm32f7x_gpio {
22+
u32_t mode;
23+
u32_t otype;
24+
u32_t ospeed;
25+
u32_t pupdr;
26+
u32_t idr;
27+
u32_t odr;
28+
u32_t bsr;
29+
u32_t lck;
30+
u32_t afr[2];
31+
};
32+
33+
union syscfg_exticr {
34+
u32_t val;
35+
struct {
36+
u16_t rsvd__16_31;
37+
u16_t exti;
38+
} bit;
39+
};
40+
41+
/* 7.2 SYSCFG registers */
42+
struct stm32f7x_syscfg {
43+
u32_t memrmp;
44+
u32_t pmc;
45+
union syscfg_exticr exticr1;
46+
union syscfg_exticr exticr2;
47+
union syscfg_exticr exticr3;
48+
union syscfg_exticr exticr4;
49+
u32_t cmpcr;
50+
};
51+
52+
#endif /* _STM32F7X_GPIO_REGISTERS_H_ */

‎arch/arm/soc/st_stm32/stm32f7/linker.ld‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
/* linker.ld - Linker command/script file */
2+
3+
/*
4+
* Copyright (c) 2018 Yurii Hamann
5+
*
6+
* SPDX-License-Identifier: Apache-2.0
7+
*/
8+
9+
#include <arch/arm/cortex_m/scripts/linker.ld>

‎arch/arm/soc/st_stm32/stm32f7/soc.c‎

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
/*
2+
* Copyright (c) 2018 Yurii Hamann
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/**
8+
* @file
9+
* @brief System/hardware module for STM32F7 processor
10+
*/
11+
12+
#include <kernel.h>
13+
#include <device.h>
14+
#include <init.h>
15+
#include <soc.h>
16+
#include <arch/cpu.h>
17+
#include <cortex_m/exc.h>
18+
19+
/**
20+
* @brief This function configures the source of stm32cube time base.
21+
* Cube HAL expects a 1ms tick which matches with k_uptime_get_32.
22+
* Tick interrupt priority is not used
23+
* @return HAL status
24+
*/
25+
uint32_t HAL_GetTick(void)
26+
{
27+
return k_uptime_get_32();
28+
}
29+
30+
/**
31+
* @brief Perform basic hardware initialization at boot.
32+
*
33+
* This needs to be run from the very beginning.
34+
* So the init priority has to be 0 (zero).
35+
*
36+
* @return 0
37+
*/
38+
static int st_stm32f7_init(struct device *arg)
39+
{
40+
u32_t key;
41+
42+
ARG_UNUSED(arg);
43+
44+
key = irq_lock();
45+
46+
_ClearFaults();
47+
48+
/* Install default handler that simply resets the CPU
49+
* if configured in the kernel, NOP otherwise
50+
*/
51+
NMI_INIT();
52+
53+
irq_unlock(key);
54+
55+
/* Update CMSIS SystemCoreClock variable (HCLK) */
56+
/* At reset, system core clock is set to 25 MHz from HSI */
57+
SystemCoreClock = 25000000;
58+
59+
return 0;
60+
}
61+
62+
SYS_INIT(st_stm32f7_init, PRE_KERNEL_1, 0);

0 commit comments

Comments
 (0)