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lines changed Original file line number Diff line number Diff line change 66
77/* AHB clocks must respect the minimum ratio AHB / DCMI_PIXCLK of 2.5 (AN5020 - Rev 3).
88 * The OV2640 PCLK is around 72 MHz for QQVGA resolution (160x120) with MCO1_SEL_HSI48
9-  * and MCO1_PRE_DIV_4 .
9+  * and MCO_PRE_DIV_4 .
1010 */
1111&rcc {
1212	clocks = <&pll>;
1919	d3ppre = <2>;
2020};
2121
22- /* See reference manual (RM0433 Rev 8) page 390:
23-  *   100: HSI48 clock selected (hsi48_ck)
24-  */
25- #define MCO1_SEL_HSI48 4
26- 
27- /* See reference manual (RM0433 Rev 8) page 391:
28-  *   0100: division by 4
29-  */
30- #define MCO1_PRE_DIV_4 4
31- 
3222&mco1 {
3323	status = "okay";
3424	clocks = <&rcc STM32_SRC_HSI48 MCO1_SEL(MCO1_SEL_HSI48)>;
35- 	prescaler = <MCO1_PRE(MCO1_PRE_DIV_4 )>;
25+ 	prescaler = <MCO1_PRE(MCO_PRE_DIV_4 )>;
3626	pinctrl-0 = <&rcc_mco_1_pa8>;
3727	pinctrl-names = "default";
3828};
    
 
   
 
     
   
   
          
     
  
    
     
 
    
      
     
 
     
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