Implement tickless capability for xlnx_psttc_timer

[stephanosio]

The xlnx_psttc_timer (drivers/timer/xlnx_psttc_timer.c) system timer driver only implements tickful timer API at this time.

Since tickless timer API is required for most tests to function properly, this feature should be implemented in order to expand the range of tests that can run on qemu_cortex_r5.

At the same time, fix any bugs and/or non-standard behaviours that cause test failures in this timer driver.

[stephanosio]

@wjliang According to the Zynq UltraScale+ TRM, the TTC implements 32-bit counters; while both the Cadence TTC IP datasheet (I-IPA01-0028-USR Rev 06) and the current xlnx_psttc_timer.c implementation suggest that the TTC counter is only 16-bit wide.

Could you advise on which is correct?

[stephanosio]

For future reference, found the answer on the Xilinx Wiki
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841648/TTC+Standalone+Driver

Modified XTtcPs_GetCounterValue,XTtcPs_GetInterval and XTtcPs_CalcIntervalFromFreq functions to use 32 bit counter/interval values for Zynq Ultrascale+ MPSoC

Fixed bug in XTtcPs_CalcIntervalFromFreq API to use correct maximum interval count (32 bit) for ZynqMP.

Three independent 32-bit timer/counters for ZynqMP and 16-bit timer/counter for Zynq

[stephanosio]

The timing of the Xilinx QEMU PS TTC emulation was found to be simply too unstable to support tickless mode operation.

Since the primary motive of this issue was to support CI validation of the tests that require tickless mode and this is not possible due to the inherent limitations in the Xilinx QEMU, this issue is going to be indefinitely postponed.

[stephanosio]

Re-opening since the QEMU icount mode allows stable emulation of the TTC timer "match" mode.