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i2c: cadence: Avoid fifo clear after start
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The Driver unintentionally programs ctrl reg to clear the fifo, which
happens after the start of transaction. Previously, this was not an issue
as it involved read-modified-write. However, this issue breaks i2c reads
on QEMU, as i2c-read is executed before guest starts programming control
register.

Fixes: ff0cf7b ("i2c: cadence: Remove unnecessary register reads")
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
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saipava authored and Andi Shyti committed May 5, 2024
1 parent dd5a440 commit c2e55b4
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1 change: 1 addition & 0 deletions drivers/i2c/busses/i2c-cadence.c
Original file line number Diff line number Diff line change
Expand Up @@ -633,6 +633,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id)

if (hold_clear) {
ctrl_reg &= ~CDNS_I2C_CR_HOLD;
ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO;
/*
* In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size
* register reaches '0'. This is an IP bug which causes transfer size
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